CY7C1355B-133AC Cypress Semiconductor Corp, CY7C1355B-133AC Datasheet - Page 7

• Manufacturer Part Number: CY7C1355B-133AC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C1355B-133AC

• Density: 9Mb
• Access Time (max): 6.5ns
• Sync/async: Synchronous
• Architecture: SDR
• Clock Freq (max): 133MHz
• Operating Supply Voltage (typ): 3.3V
• Address Bus: 18b
• Package Type: TQFP
• Operating Temp Range: 0C to 70C
• Number Of Ports: 1
• Supply Current: 250mA
• Operating Supply Voltage (min): 3.135V
• Operating Supply Voltage (max): 3.63V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 100
• Word Size: 36b
• Number Of Words: 256K
• Lead Free Status / Rohs Status: Not Compliant

Document #: 38-05117 Rev. *C
CY7C1355B–Pin Definitions
A
BW
BW
WE
ADV/LD
CLK
CE
CE
CE
OE
CEN
ZZ
0
, A
Name
1
2
3
A
C
, BW
, BW
1
, A
B
D
37,36,32,33,
34,35,44,45,
46,47,48,49,
50,81,82,83,
93,94,95,96 L5,G5,G3,
99,100
TQFP
88
85
89
98
97
92
86
87
64
P4,N4,A2,
C2,R2,A3,
G4,T4,A5,
B3,C3,T3,
B5,C5,T5,
A6,C6,R6
BGA
M4
H4
B4
K4
E4
B2
B6
L3
F4
T7
R9,R10,R11
A9,A10,B2,
B10,P3,P4,
P8,P9,P10,
R3,R4,R8,
R6,P6,A2,
B5,A5,A4,
fBGA
H11
B4
B7
A8
B6
A3
B3
A6
B8
A7
Asynchronous
Asynchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Input-
Input-
Input-
Input-
Input-
Clock
Input-
Input-
Input-
Input-
Input-
Input-
I/O
Address Inputs used to select one of the 256K
address locations. Sampled at the rising edge of the
CLK. A
Byte Write Inputs, active LOW. Qualified with WE to
conduct Writes to the SRAM. Sampled on the rising edge
of CLK.
Write Enable Input, active LOW. Sampled on the rising
edge of CLK if CEN is active LOW. This signal must be
asserted LOW to initiate a write sequence.
Advance/Load Input. Used to advance the on-chip ad-
dress counter or load a new address. When HIGH (and
CEN is asserted LOW) the internal burst counter is ad-
vanced. When LOW, a new address can be loaded into
the device for an access. After being deselected, ADV/LD
should be driven LOW in order to load a new address.
Clock Input. Used to capture all synchronous inputs to
the device. CLK is qualified with CEN. CLK is only recog-
nized if CEN is active LOW.
Chip Enable 1 Input, active LOW. Sampled on the rising
edge of CLK. Used in conjunction with CE
select/deselect the device.
Chip Enable 2 Input, active HIGH. Sampled on the rising
edge of CLK. Used in conjunction with CE
select/deselect the device.
Chip Enable 3 Input, active LOW. Sampled on the rising
edge of CLK. Used in conjunction with CE
select/deselect the device.
Output Enable, asynchronous input, active LOW.
Combined with the synchronous logic block inside the de-
vice to control the direction of the I/O pins. When LOW,
the I/O pins are allowed to behave as outputs. When
deasserted HIGH, I/O pins are three-stated, and act as
input data pins. OE is masked during the data portion of
a write sequence, during the first clock when emerging
from a deselected state, when the device has been dese-
lected.
Clock Enable Input, active LOW. When asserted LOW
the Clock signal is recognized by the SRAM. When deas-
serted HIGH the Clock signal is masked. Since deassert-
ing CEN does not deselect the device, CEN can be used
to extend the previous cycle when required.
ZZ “Sleep” Input. This active HIGH input places the de-
vice in a non-time critical “sleep” condition with data integ-
rity preserved. During normal operation, this pin can be
connected to V
[1:0]
are fed to the two-bit burst counter.
SS
or left floating.
Description
CY7C1355B
CY7C1357B
2
1
1
, and CE
and CE
and CE
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