71V3579S85BG IDT, Integrated Device Technology Inc, 71V3579S85BG Datasheet - Page 2

• Manufacturer Part Number: 71V3579S85BG
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of 71V3579S85BG

• Density: 4.5Mb
• Access Time (max): 8.5ns
• Sync/async: Synchronous
• Architecture: SDR
• Clock Freq (max): 87MHz
• Operating Supply Voltage (typ): 3.3V
• Address Bus: 18b
• Package Type: BGA
• Operating Temp Range: 0C to 70C
• Number Of Ports: 1
• Supply Current: 180mA
• Operating Supply Voltage (min): 3.135V
• Operating Supply Voltage (max): 3.465V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 119
• Word Size: 18b
• Number Of Words: 256K
• Lead Free Status / Rohs Status: Not Compliant

NOTE:
1. All synchronous inputs must meet specified setup and hold times with respect to CLK.
IDT71V3577, IDT71V3579, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
3.3V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect
I/O
BW
I/O
Symbol
A
ADSC
ADSP
BWE
V
ADV
CLK
P1
LBO
CS
V
CS
GW
V
0
OE
CE
0
NC
1
ZZ
DDQ
-A
-I/O
DD
-BW
SS
-I/O
1
0
17
31
P4
4
Linear Burst Order
Byte Write Enable
Data Input/Output
(Cache Controller)
Address Status
Address Status
Address Inputs
Individual Byte
Output Enable
Burst Address
Write Enables
Power Supply
Power Supply
Pin Function
Chip Select 0
Chip Select 1
Chip Enable
Global Write
No Connect
Sleep Mode
(Processor)
Advance
Ground
Enable
Clock
N/A
N/A
N/A
N/A
I/O
I/O
1
I
I
I
I
I
I
I
I
I
I
I
I
I
Active
HIGH
HIGH
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
LOW
N/A
N/A
N/A
N/A
N/A
N/A
N/A
I/O pins if the chip is also selected. When OE is HIGH the I/O pins are in a high-impedance
IDT71V3577/79 to its lowest power consumption level. Data retention is guaranteed in
Synchronous Address inputs. The address register is triggered by a combi-nation of the rising
edge of CLK and ADSC Low or ADSP Low and CE Low.
Synchronous Address Status from Cache Controller. ADSC is an active LOW input that is
used to load the address registers with new addresses.
Synchronous Address Status from Processor. ADSP is an active LOW input that is used to
load the address registers with new addresses. ADSP is gated by CE.
Synchronous Address Advance. ADV is an active LOW input that is used to advance the
internal burst counter, controlling burst access after the initial address is loaded. When the
input is HIGH the burst counter is not incremented; that is, there is no address advance.
Synchronous byte write enable gates the byte write inputs BW
rising edge of CLK then BWx inputs are passed to the next stage in the circuit. If BWE is
HIGH then the byte write inputs are blocked and only GW can initiate a write cycle.
Synchronous byte write enables. BW
Any active byte write causes all outputs to be disabled.
Synchronous chip enable. CE is used with CS
also gates ADSP.
This is the clock input. All timing references for the device are made with respect to this
input.
Synchronous active HIGH chip select. CS
Synchronous active LOW chip select. CS
Synchronous global write enable. This input will write all four 9-bit data bytes when LOW on
the rising edge of CLK. GW supersedes individual byte write enables.
Synchronous data input/output (I/O) pins. The data input path is registered, triggered by the
rising edge of CLK. The data output path is flow-through (no output register).
Asynchronous burst order selection input. When LBO is HIGH, the inter-leaved burst
sequence is selected. When LBO is LOW the Linear burst sequence is selected. LBO is a
static input and must not change state while the device is operating.
Asynchronous output enable. When OE is LOW the data output drivers are enabled on the
state.
3.3V core power supply.
3.3V I/O Supply.
Ground.
NC pins are not electrically connected to the device.
Asynchronous sleep mode input. ZZ HIGH will gate the CLK internally and power down the
Sleep Mode.
6.42
2
Commercial and Industrial Temperature Ranges
1
controls I/O
Description
1
0
is used with CE and CS
is used with CE and CS
0
and CS
0-7
, I/O
1
to enable the IDT71V3577/79. CE
P1
, BW
1
-BW
2
controls I/O
0
1
4
. If BWE is LOW at the
to enable the chip.
to enable the chip.
8-15
, I/O
P2
5280 tbl 02
, etc.