61298SA15Y IDT, Integrated Device Technology Inc, 61298SA15Y Datasheet - Page 6

• Manufacturer Part Number: 61298SA15Y
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of 61298SA15Y

• Density: 256Kb
• Access Time (max): 15ns
• Sync/async: Asynchronous
• Architecture: Not Required
• Clock Freq (max): Not RequiredMHz
• Operating Supply Voltage (typ): 5V
• Address Bus: 16b
• Package Type: SOJ
• Operating Temp Range: 0C to 70C
• Number Of Ports: 1
• Supply Current: 140mA
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 28
• Word Size: 4b
• Number Of Words: 64K
• Lead Free Status / Rohs Status: Not Compliant

Timing Waveform of Write Cycle No. 1 (WE Controlled Timing)
ADDRESS
Timing Waveform of Write Cycle No. 2 (CS Controlled Timing)
ADDRESS
NOTES:
1. A write occurs during the overlap of a LOW CS and a LOW WE.
2. OE is continuously HIGH. If OE is LOW during a WE controlled write cycle, the write pulse width must be the greater than or equal to t
3. During this period, I/O pins are in the output state so that the input signals must not be applied.
4. If the CS LOW transition occurs simultaneously with or after the WE LOW transition, the outputs remain in a high-impedance state.
5. Transition is measured ±200mV from steady state.
DATA
IDT61298SA
CMOS Static RAM 256K (64K x 4-Bit)
DATA
DATA
to turn off and data to be placed on the bus for the required t
write pulse is as short as the spectified t
OUT
WE
WE
CS
CS
IN
IN
t
AS
t
AS
WP
(3)
.
t
WHZ
DW
(5)
. If OE is HIGH during a WE controlled write cycle, this requirement does not apply and the minimum
t
AW
t
AW
t
WP
t
WC
t
t
WC
CW
(2)
6
t
DW
DATA VALID
t
DW
DATA VALID
t
DH
t
WR
t
OW
t
WR
(5)
Commercial Temperature Range
t
DH
WHZ
+ t
(1,4)
DW
(1,2,4)
(3)
to allow the I/O drivers
2971 drw 08
2971 drw 09
,
,