71V3578S133BG IDT, Integrated Device Technology Inc, 71V3578S133BG Datasheet - Page 11

• Manufacturer Part Number: 71V3578S133BG
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of 71V3578S133BG

• Density: 4.5Mb
• Access Time (max): 4.2ns
• Sync/async: Synchronous
• Architecture: SDR
• Clock Freq (max): 133MHz
• Operating Supply Voltage (typ): 3.3V
• Address Bus: 18b
• Package Type: BGA
• Operating Temp Range: 0C to 70C
• Number Of Ports: 1
• Supply Current: 250mA
• Operating Supply Voltage (min): 3.135V
• Operating Supply Voltage (max): 3.465V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 119
• Word Size: 18b
• Number Of Words: 256K
• Lead Free Status / Rohs Status: Not Compliant

NOTES:
1. L = V
2. BW
3. Multiple bytes may be selected during the same cycle.
NOTES:
1. L = V
2. Synchronous function pins must be biased appropriately to satisfy operation requirements.
NOTE:
1. Upon completion of the Burst sequence the counter wraps around to its initial state.
NOTE:
1. Upon completion of the Burst sequence the counter wraps around to its initial state.
First Address
Second Address
Fourth Address
First Address
Second Address
Fourth Address
Third Address
Third Address
IDT71V3576, IDT71V3578, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
3.3V I/O, Pipelined Outputs, Burst Counter, Single Cycle Deselect
3
and BW
IL
IL
Write all Bytes
Write all Bytes
Write Byte 1
Write Byte 2
Write Byte 3
Write Byte 4
, H = V
, H = V
Operation
Read
Read
4
(1)
(1)
are not applicable for the IDT71V3578.
IH
IH
Sleep Mode
Operation
Deselected
, X = Don’t Care.
, X = Don’t Care.
Read
Read
Write
(3)
(3)
(3)
(3)
(2)
GW
H
H
H
H
H
H
H
L
OE
H
X
X
X
L
A1
A1
0
0
0
0
1
1
1
1
Sequence 1
Sequence 1
BWE
H
X
L
L
L
L
L
L
LBO
A0
A0
0
0
0
0
1
1
1
1
ZZ
6.42
LBO
L
L
L
L
H
11
BW
X
X
H
L
L
H
H
H
A1
A1
0
0
0
0
1
1
1
1
1
Sequence 2
Sequence 2
A0
A0
0
0
0
0
1
1
1
1
Commercial and Industrial Temperature Ranges
BW
High-Z – Data In
X
X
H
L
H
L
H
H
I/O Status
2
Data Out
High-Z
High-Z
High-Z
A1
A1
0
0
0
0
1
1
1
1
Sequence 3
Sequence 3
A0
A0
BW
0
0
0
0
1
1
1
1
X
X
H
H
H
L
H
L
3
A1
A1
0
0
0
0
1
1
1
1
Sequence 4
Sequence 4
Standby
Power
Active
Active
Active
Sleep
BW
X
H
X
H
H
H
L
L
4
5279 tbl 12
5279 tbl 13
5279 tbl 14
5279 tbl 15
A0
A0
0
0
0
0
1
1
1
1