K6R4008V1D-UI10 Samsung Semiconductor, K6R4008V1D-UI10 Datasheet
K6R4008V1D-UI10
Specifications of K6R4008V1D-UI10
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K6R4008V1D-UI10 Summary of contents
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... K6R4008V1D Document Title 512Kx8 Bit High Speed Static RAM(3.3V Operating). Operated at Commercial and Industrial Temperature Ranges. Revision History Rev No. History Rev. 0.0 Initial release with Preliminary. Rev. 0.1 Add Low Ver. Rev. 0.2 Change Icc, Isb and Isb1 Item I CC(Commercial) I CC(Industrial) ...
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... K6R4008V1D 4Mb Async. Fast SRAM Ordering Information Org. Part Number K6R4004C1D-J(K)C( K6R4004V1D-J(K)C(I) 08/10 K6R4008C1D-J(K,T,U)C(I) 10 512K x8 K6R4008V1D-J(K,T,U)C(I) 08/10 K6R4016C1D-J(K,T,U,E)C(I) 10 256K x16 K6R4016V1D-J(K,T,U,E)C(I,L,P) 08/10 VDD(V) Speed ( ns ) PKG 32-SOJ K : 32-SOJ(LF) 3.3 8/ 36-SOJ K : 36-SOJ(LF 44-TSOP2 3.3 8/ 44-TSOP2(LF 44-SOJ K : 44-SOJ(LF 44-TSOP2 U : 44-TSOP2(LF) 3.3 8/ 48-TBGA - 2 - PRELIMINARY CMOS SRAM Temp. & ...
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... The K6R4008V1D is a 4,194,304-bit high-speed Static Random Access Memory organized as 524,288 words by 8 bits. The K6R4008V1D uses 8 common input and output lines and has an output enable pin which operates faster than address access time at read cycle. The device is fabricated using SAMSUNG′s advanced CMOS process and designed for high-speed circuit technology ...
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... K6R4008V1D PIN CONFIGURATION (Top View I I 36-SOJ Vcc 9 Vss PIN FUNCTION Pin Name Pin Function Address Inputs Write Enable CS Chip Select OE Output Enable I/O ~ I/O Data Inputs/Outputs Power(+3.3V Ground SS N.C No Connection ABSOLUTE MAXIMUM RATINGS* Parameter Voltage on Any Pin Relative to V ...
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... K6R4008V1D RECOMMENDED DC OPERATING CONDITIONS* Parameter Supply Voltage Ground Input High Voltage Input Low Voltage * The above parameters are also guaranteed at industrial temperature range. (Min) = -2.0V a.c(Pulse Width ≤ 8ns) for I ≤ 20mA 2.0V a.c (Pulse Width ≤ 8ns) for I ≤ 20mA ...
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... 1.5V L 30pF* * Including Scope and Jig Capacitance K6R4008V1D-08 Symbol Min Max OLZ OHZ PRELIMINARY CMOS SRAM Value 3ns 1.5V See below , & WHZ OW OLZ OHZ +3.3V 319Ω D OUT 353Ω 5pF* K6R4008V1D-10 Min Max - Unit Rev. 2.0 July 2004 ...
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... Min Max WP1 WHZ (Address Controlled CS=OE (WE OLZ t LZ(4, 50% (Max.) is less than PRELIMINARY CMOS SRAM K6R4008V1D-10 Min Max WE Valid Data t HZ(3,4,5) t OHZ t DH Valid Data t PD 50% (Min.) both for a given device and from device to LZ Unit Rev. 2.0 July 2004 ...
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... K6R4008V1D TIMING WAVEFORM OF WRITE CYCLE(1) Address Data in Data out TIMING WAVEFORM OF WRITE CYCLE(2) Address CS WE Data in Data out TIMING WAVEFORM OF WRITE CYCLE(3) Address CS WE High-Z Data in High-Z Data out (OE= Clock CW(3) t AS(4) High-Z t OHZ(6) (OE=Low Fixed CW( AS(4) WP1(2) High-Z t WHZ(6) (CS = Controlled) ...
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... K6R4008V1D NOTES(WRITE CYCLE) 1. All write cycle timing is referenced from the last valid address to the first transition address write occurs during the overlap of a low CS and WE. A write begins at the latest transition CS going low and WE going low ; A write ends at the earliest transition CS going high or WE going high ...
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... K6R4008V1D PACKAGE DIMENSIONS 36-SOJ-400 #36 11.18 ±0.12 0.440 ±0.005 #1 +0.10 0.43 -0.05 +0.004 0.017 0.95 -0.002 ( ) 0.0375 44-TSOP2-400BF #44 #1 18.81 0.741 18.41 0.725 +0.10 0.30 0.805 −0. +0.004 0.012 0.032 −0.002 23.90 MAX 0.941 23.50 ±0.12 0.925 ±0.005 +0.10 0.71 1.27 -0.05 +0 ...