PSB4860HV4.1 Lantiq, PSB4860HV4.1 Datasheet - Page 102

• Manufacturer Part Number: PSB4860HV4.1
• Manufacturer: Lantiq

Specifications of PSB4860HV4.1

• Lead Free Status / Rohs Status: Supplier Unconfirmed

Data Sheet
2.3.3
The can be in either reset mode, power down mode or active mode. During reset the
clears the hardware configuration registers and stops both internal and external activity.
The address lines MA
lines (strong outputs) or auxiliary port pins (I/O). In reset mode the hardware
configuration registers can be read and written. With the first access to a read/write
register the enters active mode. In this mode the main oscillator is running and normal
operation takes place. By setting the power down bit (PD) the can be brought to power
down mode.
Table 78
Register # of Bits
CCTL
In power down mode the main oscillator is stopped and, depending on
HWCONFIG2:PPM), the memory control lines are released (weak high). Given that the
auxiliary oscillator is still active and enabled (bit OSC in register HWCONFIG0), then
depending on the configuration (ARAM/DRAM, APP), the may still generate external
activity (e.g. refresh cycles). The enters active mode again upon an access to a read/
write register. Figure 48 shows a state chart of the modes of the .
Figure 48 Operation Modes - State Chart
2.3.4
The can generate an interrupt to inform the host of an update of the STATUS register
according to table 79. An interrupt mask register (INTM) can be used to disable or enable
the interrupting capability of each bit of the STATUS register except ABT individually.
1
Reset and Power Down Mode
Power Down Bit
Interrupt
0
Name
PD
-MA
R/W reg. access
15
Active
Mode
provide a weak low until they are actually used as address
Comment
power down mode
R/W reg. access
CCTL.PD=1
RST=1
Reset
Mode
102
RST=1
Power Down
Mode
PSB 4860
2000-01-14