ATA5811-PLQX Atmel, ATA5811-PLQX Datasheet - Page 53

• Manufacturer Part Number: ATA5811-PLQX
• Manufacturer: Atmel

Specifications of ATA5811-PLQX

• Operating Temperature (min): -40C
• Operating Temperature (max): 105C
• Operating Temperature Classification: Industrial
• Product Depth (mm): 7mm
• Product Height (mm): 0.9mm
• Product Length (mm): 7mm
• Lead Free Status / Rohs Status: Compliant

Figure 44. Timing Diagram During Bit-check
4689B–RKE–04/04
Bit-check counter
Demod_Out
RX_ACTIVE
(Lim_min = 14, Lim_max = 24)
Bit check
T
Start-up mode
Startup_Sig_Proc
0
For the best noise immunity it is recommended to use a low span between T
T
preburst. A '11111...' or a '10101...' sequence in Manchester or Bi-phase is a good
choice concerning that advice. A good compromise between sensitivity and susceptibil-
ity to noise regarding the expected edge to edge time t
get the maximum sensitivity the time window should be ±50% and then N
Using preburst patterns that contain various edge to edge time periods, the Bit-check
limits must be programmed according to the required span.
The Bit-check limits are determined by means of the formula below:
T
T
Lim_min is defined by the bits Lim_min 0 to Lim_min 5 in control register 5.
Lim_max is defined by the bits Lim_max 0 to Lim_max 5 in control register 6.
Using the above formulas, Lim_min and Lim_max can be determined according to the
required T
is T
“Receiving Mode”. The lower limit should be set to Lim_min
the upper limit is Lim_max = 63.
Figure 44, Figure 45 on page 54, and Figure 46 on page 54 illustrate the Bit-check for
the Bit-check limits Lim_min = 14 and Lim_max = 24. The signal processing circuits are
enabled during T
(Demod_Out) is undefined during that period. When the Bit-check becomes active, the
Bit-check counter is clocked with the cycle T
Figure 44 shows how the Bit-check proceeds if the Bit-check counter value CV_Lim is
within the limits defined by Lim_min and Lim_max at the occurrence of a signal edge. In
Figure 45 on page 54 the Bit-check fails as the value CV_Lim is lower than the limit
Lim_min. The Bit-check also fails if CV_Lim reaches Lim_max. This is illustrated in Fig-
ure 46 on page 54.
1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 9 101112131415161718 1 2 3 4 5 6 7 8 9 10 11
Lim_max
Lim_min
Lim_max
XDCLK
. This is achieved using a fixed frequency at a 50% duty cycle for the transmitter
= Lim_min
= (Lim_max - 1)
. The minimum edge to edge time t
Lim_min
T
XDCLK
, T
Startup_PLL
Lim_max
T
XDCLK
1/2 Bit
ATA5811/ATA5812 [Preliminary]
and T
and T
T
XDCLK
XDCLK
Startup_Sig_Proc
Bit-check mode
Bit check ok
T
. The time resolution defining T
Bit-check
XDCLK
. The output of the ASK/FSK demodulator
ee
.
is defined according to the section
1/2 Bit
ee
is a time window of ±38%, to
12131415 1 2 3 4
Bit check ok
10. The maximum value of
Lim_min
1/2 Bit
5 6 7
and T
Bit-check
Lim_min
Lim_max
and
53
6.