GAL20V8B-25LP Lattice, GAL20V8B-25LP Datasheet - Page 20
GAL20V8B-25LP
Manufacturer Part Number
GAL20V8B-25LP
Description
SPLD - Simple Programmable Logic Devices 5V 20 I/O
Manufacturer
Lattice
Datasheet
1.GAL20V8B-10LP.pdf
(27 pages)
Specifications of GAL20V8B-25LP
Logic Family
GAL
Number Of Macrocells
8
Maximum Operating Frequency
41.7 MHz
Number Of Programmable I/os
8
Delay Time
25 ns
Operating Supply Voltage
5 V
Supply Current
90 mA
Maximum Operating Temperature
+ 75 C
Minimum Operating Temperature
0 C
Package / Case
PDIP-24
Mounting Style
Through Hole
Number Of Product Terms Per Macro
8
Supply Voltage (max)
5.25 V
Supply Voltage (min)
4.75 V
Lead Free Status / Rohs Status
No
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
GAL20V8B-25LP
Manufacturer:
LAITTICE
Quantity:
1 872
Part Number:
GAL20V8B-25LP
Manufacturer:
LATTICE
Quantity:
20 000
Company:
Part Number:
GAL20V8B-25LPI
Manufacturer:
MICRON
Quantity:
3 400
Company:
Part Number:
GAL20V8B-25LPI
Manufacturer:
LATTICE
Quantity:
500
Company:
Part Number:
GAL20V8B-25LPN
Manufacturer:
LAITTICE
Quantity:
1 900
Part Number:
GAL20V8B-25LPN
Manufacturer:
LATTICE
Quantity:
20 000
Circuitry within the GAL20V8 provides a reset signal to all registers
during power-up. All internal registers will have their Q outputs set
low after a specified time (
the registered output pins (if they are enabled) will always be high
on power-up, regardless of the programmed polarity of the output
pins. This feature can greatly simplify state machine design by pro-
viding a known state on power-up. Because of the asynchronous
nature of system power-up, some conditions must be met to provide
Typ. Vref = 3.2V
Power-Up Reset
Input/Output Equivalent Schematics
PIN
PIN
ESD
Protection
Circuit
ESD
Protection
Circuit
Vcc
Typical Input
FEEDBACK/EXTERNAL
t
pr, 1μs MAX). As a result, the state on
INTERNAL REGISTER
OUTPUT REGISTER
Active Pull-up
Circuit
Vref
Q - OUTPUT
CLK
Vcc
Vcc
Vcc (min.)
Vcc
18
t
pr
a valid power-up reset of the device. First, the V
monotonic. Second, the clock input must be at static TTL level as
shown in the diagram during power up. The registers will reset
within a maximum of
clocking the device until all input and feedback path setup times
have been met. The clock must also meet the minimum pulse width
requirements.
Typ. Vref = 3.2V
Data
Output
Internal Register
Reset to Logic "0"
Device Pin
Reset to Logic "1"
t
wl
Tri-State
Control
t
su
Specifications GAL20V8
Feedback
t
pr time. As in normal system operation, avoid
Typical Output
Vcc
Active Pull-up
Circuit
Feedback
(To Input Buffer)
Vref
CC
rise must be
PIN
PIN