IS24C02-3Z ISSI, Integrated Silicon Solution Inc, IS24C02-3Z Datasheet - Page 4

• Manufacturer Part Number: IS24C02-3Z
• Description: EEPROM 2.5V 2Kb
• Manufacturer: ISSI, Integrated Silicon Solution Inc

Specifications of IS24C02-3Z

• Memory Size: 2 Kbit
• Organization: 256 K x 8
• Interface Type: 2-Wire
• Maximum Clock Frequency: 0.4 MHz
• Access Time: 5 ms
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2.5 V
• Maximum Operating Current: 3 mA
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Package / Case: TSSOP-8
• Minimum Operating Temperature: 0 C
• Operating Supply Voltage: 2.5 V, 5.5 V
• Operating Temperature: 0 C to + 70 C
• Lead Free Status / Rohs Status: No

DEVICE OPERATION
The IS24CXX family features a serial communication and
supports a bi-directional 2-wire bus transmission protocol.
2-WIRE BUS
The two-wire bus is defined as a Serial Data line(SDA), and
a Serial Clock Line (SCL). The protocol defines any device
that sends data onto the SDA bus as a transmitter, and the
receiving devices as a receiver. The bus is controlled by
MASTER device which generates the SCL, controls the bus
access and generates the STOP and START conditions.
The IS24CXX is the SLAVE device on the bus.
THE BUS PROTOCOL:
-- Data transfer may be initiated only when the bus is not
-- During a data transfer, the data line must remain stable
The state of the data line represents valid data when after
a START condition, the data line is stable for the duration
of the HIGH period of the clock signal. The data on the line
must be changed during the LOW period of the clock signal.
There is one clock pulse per bit of data. Each data transfer
is initiated with a START condition and terminated with a
STOP condition.
START CONDITION
The START condition precedes all commands to the
devices and is defined as a HIGH to LOW transition of SDA
when SCL is HIGH. The IS24CXX monitors the SDA and
SCL lines and will not respond until the START condition is
met.
STOP CONDITION
The STOP condition is defined as a LOW to HIGH transition
of SDA when SCL is HIGH. All operations must end with a
STOP condition.
ACKNOWLEDGE
After a successful data transfer, each receiving device is
required to generate an acknowledge. The Acknowledging
device pulls down the SDA line.
DEVICE ADDRESSING
The MASTER begins a transmission by sending a START
condition. The MASTER then sends the address of the
particular slave devices it is requesting. The SLAVE
address is 8 bytes.
The four most significant bytes of the address are fixed as
1010 for the IS24CXX.
For the IS24C16, the bytes(B2, B1 and B0) are used for
memory page addressing (the IS24C16 is organized as
eight blocks of 256 bytes).
4
IS24C01 IS24C02 IS24C04 IS24C08
busy
whenever the clock line is high. Any changes in the data
line while the clock line is high will be interpreted as a
START or STOP condition.
Integrated Silicon Solution, Inc. — www.issi.com —
For the IS24C04 out of the next three bytes, B0 is for
Memory Page Addressing (the IS24C04 is organized as two
blocks of 256 bytes) and A2 and A1 bytes are used as
device address bytes and must compare to its hard-wire
inputs pins (A2 and A1). Up to four IS24C04's may be
individually addressed by the system. The page addressing
bytes for IS24Cxx should be considered the most significant
bytes of the data word address which follows.
For the IS24C08 out of the next three bytes, B1 and B0 are
for memory page addressing (the IS24C08 is organized as
four blocks of 256 bytes) and the A2 bit is used as device
address bit and must compare to its hard-wired input pin
(A2). Up to two IS24C08 may be individually addressed by
the system. The page addressing bytes for IS24CXX
should be considered the most significant bytes of the data
word address which follows.
For the IS24C01 and IS24C02, the A0, A1, and A2 are used
as device address bytes and must compare to its hard-
wired input pins (A0, A1, and A2) Up to Eight IS24C01 and/
or IS24C02's may be individually addressed by the system.
The last bit of the slave address specifies whether a Read
or Write operation is to be performed. When this bit is set
to 1, a Read operation is selected, and when set to 0, a Write
operation is selected.
After the MASTER sends a START condition and the
SLAVE address byte, the IS24CXX monitors the bus and
responds with an Acknowledge (on the SDA line) when its
address matches the transmitted slave address. The
IS24CXX pulls down the SDA line during the ninth clock
cycle, signaling that it received the eight bytes of data. The
IS24CXX then performs a Read or Write operation depending
on the state of the R/W bit.
WRITE OPERATION
BYTE WRITE
In the Byte Write mode, the Master device sends the
START condition and the slave address information(with
the R/W set to Zero) to the Slave device. After the Slave
generates an acknowledge, the Master sends the byte
address that is to be written into the address pointer of the
IS24CXX. After receiving another acknowledge from the
Slave, the Master device transmits the data byte to be
written into the address memory location. The IS24CXX
acknowledges once more and the Master generates the
STOP condition, at which time the device begins its internal
programming cycle. While this internal cycle is in progress,
the device will not respond to any request from the Master
device.
IS24C16
ISSI
1-800-379-4774
03/24/04
Rev. F
®