H27U8G8T2BTR-BC HYNIX SEMICONDUCTOR, H27U8G8T2BTR-BC Datasheet
H27U8G8T2BTR-BC
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H27U8G8T2BTR-BC Summary of contents
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Gb NAND Flash This document is a general product description and is subject to change without notice. Hynix does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev 0.0 / Jul. 2008 8 ...
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Document Title 8 Gbit (1024 bit) NAND Flash Memory Revision History Revision No. 0.0 Initial Draft. Rev 0.0 / Jul. 2008 8 Gbit (1024 bit) NAND Flash History Preliminary H27U8G8T2B Series Draft Date Remark ...
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... Simple interface with microcontroller STATUS REGISTER - Normal Status Register (Read/Program/Erase) HARDWARE DATA PROTECTION - Device locked during Power transitions. DATA RETENTION - 5,000 Program/Erase cycles (with 4 bit / 528 byte ECC years Data Retention PACKAGE - H27U8G8T2BTR-BX : 48-Pin TSOP1 ( 1.2 mm) - H27U8G8T2BTR-BX (Lead & Halogen Free) Preliminary 3 ...
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SUMMARY DESCRIPTION Hynix NAND H27U8G8T2B Series have 1024 bit with spare bit capacity. The device is offered in 3.3 V Vcc Power Supply, and with x8 I/O interface. Its NAND cell provides ...
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Figure 1 : Logic Diagram Figure 2 : 48-TSOP1 Contact, x8 Device Rev 0.0 / Jul. 2008 Preliminary H27U8G8T2B Series 8 Gbit (1024 bit) NAND Flash IO7 - IO0 Data Input / Outputs CLE Command latch enable ...
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PIN DESCRIPTION Pin Name DATA INPUTS/OUTPUTS The IO pins allow to input command, address and data and to output data during read / program IO0 ~ IO7 operations. The inputs are latched on the rising edge of Write Enable ...
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Plane 0 2 1024 Blocks . per Plane . 2048 Blocks . per device 2044 2046 Page Buffer 4K Bytes 1st Cycle 2nd Cycle 3rd Cycle 4th Cycle 5th Cycle NOTE must be set to Low. 2. ...
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FUNCTION PAGE READ MULTI-PLANE READ READ FOR COPY-BACK MULTIPLANE READ FOR COPYBACK READ ID RESET PAGE PROGRAM COPY BACK PROGRAM MULTI-PLANE PROGRAM MULTI-PLANE COPY BACK PROGRAM BLOCK ERASE MULTI-PLANE BLOCK ERASE READ STATUS REGISTER RANDOM DATA INPUT RANDOM DATA OUTPUT ...
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BUS OPERATION There are six standard bus operations that control the device. These are Command Input, Address Input, Data Input, Data Output, Write Protect, and Standby. Typically glitches less than Chip Enable, Write Enable and Read ...
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DEVICE OPERATION 3.1 Page Read. Upon initial power up, the device defaults to Read mode. This operation is also initiated by writing 00h and 30h to the command register along with five address cycles. After a 1st page read ...
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Page Program The device is programmed by page. Only a single partial or complete page programming operation within the same page, without an intervening erase operation, is allowed The addressing must be done in sequential order in a block. ...
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Multiplane Block Erase Multiple plane erase allows parallel erase of two blocks, one per each plane. Block erase setup command (60h) must be repeated two times, each time followed by 1st and 2nd block address cycles respectively (3 cycles ...
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Read ID The device contains a product identification mode, initiated by writing 90h to the command register, followed by an ad- dress input of 00h. Five read cycles sequentially output the manufacturer code (20h), and the device code and ...
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OTHER FEATURES 4.1 Data Protection The device is designed to offer protection from any involuntary program/erase during power-transitions. An internal volt- age detector disables all functions whenever Vcc is below about 2 pin provides hardware protection and ...
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Parameter Valid Block Number NOTE: 1. The 1st block is guaranteed valid block at the time of shipment. Symbol Ambient Operating Temperature (Temperature Range Option Ambient Operating Temperature (Temperature Range Option 6) T BIAS ...
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A30 ~ A0 ADDRESS REGISTER/ COUNTER PROGRAM ERASE CONTROLLER HV GENERATION ALE CLE WE CE COMMAND INTERFACE WP LOGIC RE COMMAND REGISTER DATA REGISTER Rev 0.0 / Jul. 2008 8 Gbit (1024 bit) NAND Flash 8192 Mbit ...
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Parameter Symbol Sequential I CC1 Read Operating I Program Current CC2 I Erase CC3 I Stand-by Current (TTL) CC4 I Stand-By Current (CMOS) CC5 I Input Leakage Current LI I Output Leakage Current LO V Input High Voltage IH V ...
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Item Input / Output Capacitance Input Capacitance Table 10 : Pin Capacitance ( Parameter Program Time / Multiplane Program Time Dummy Busy Time for Multiplane Program Number of partial Program Cycles in the same page Block Erase Time ...
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Parameter CLE Setup time CLE Hold time CE Setup time CE Hold time WE Pulse width ALE Setup time ALE Hold time Data Setup time Data Hold time Write Cycle time WE High Hold time Address to Data Loading time ...
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IO Page Program 0 Pass / Fail Plane 0 1 Pass / Fail Plane 1 2 Pass / Fail Ready/Busy 6 Ready/Busy 7 Write Protect Table 13 : Status Register Coding DEVICE IDENTIFIER BYTE st ...
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Description 1 2 Die / Package bit / cell 2 bit / cell Cell Type 3 bit / cell 4 bit / cell 1 Number of 2 Simultaneously 4 Programmed Pages 8 Interleave Program Not Supported Between ...
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Planes Plane Size (without Spare) Reserved Table 18 : 5th Byte of Device Identifier Description Rev 0.0 / Jul. 2008 8 Gbit (1024 bit) NAND Flash Description DQ7 DQ6-5 512Mb ...
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Figure 5 : Command Latch Cycle Rev 0.0 / Jul. 2008 8 Gbit (1024 bit) NAND Flash Figure 6 : Address Latch Cycle Preliminary H27U8G8T2B Series 23 ...
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CLE CE tALS ALE tWP WE tDS I/Ox Figure 7 : Input Data Latch Cycle CE tREA RE I/Ox tRR R/B Figure 8 : Sequential Out Cycle after Read (CLE = ALE = L) Rev 0.0 ...
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Figure 9 : Sequential Out Cycle after Read (EDO type CLE = ALE = L) Figure 10 : Read Status Register Rev 0.0 / Jul. 2008 Preliminary H27U8G8T2B Series 8 Gbit (1024 bit) ...
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CLE ALE RE I/Ox 00h Col.Add1 Col.Add2 Row Add1 Row Add2 Row Add3 Column Address R/D Figure 11 : Page Read Operation CLE CE WE ALE RE Col. Col. I/Ox 00h Add1 Add2 Column Address R/B ...
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Figure 13 : Random Data Output Rev 0.0 / Jul. 2008 Preliminary H27U8G8T2B Series 8 Gbit (1024 bit) NAND Flash 27 ...
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Figure 14 : Multiplane Read Operation with Random Data Output Rev 0.0 / Jul. 2008 Preliminary H27U8G8T2B Series 8 Gbit (1024 bit) NAND Flash 28 ...
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Figure 15 : Page Program Operation Rev 0.0 / Jul. 2008 Preliminary H27U8G8T2B Series 8 Gbit (1024 bit) NAND Flash 29 ...
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Figure 16 : Multiplane Page Program Rev 0.0 / Jul. 2008 Preliminary H27U8G8T2B Series 8 Gbit (1024 bit) NAND Flash 30 ...
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Rev 0.0 / Jul. 2008 8 Gbit (1024 bit) NAND Flash Figure 17 : Random Data Input Preliminary H27U8G8T2B Series 31 ...
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Rev 0.0 / Jul. 2008 8 Gbit (1024 bit) NAND Flash Figure 18 : Block Erase Preliminary H27U8G8T2B Series 32 ...
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CLE CE tWC WE ALE RE I/Ox Row Add3 60h Row Add1 Row Add2 Row Address R/B Block Erase Setup Command1 Block Erase Setup Command2 Ex.) Address Restriction for Multi-Plane Block Erase Operation R/B I/O0~7 Address 60h 60h Row Add1,2,3 ...
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Figure 20 : Copy Back Program Operation Rev 0.0 / Jul. 2008 Preliminary H27U8G8T2B Series 8 Gbit (1024 bit) NAND Flash 34 ...
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Figure 21 : Copy Back with Random Data Input Rev 0.0 / Jul. 2008 Preliminary H27U8G8T2B Series 8 Gbit (1024 bit) NAND Flash 35 ...
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R/B I/Ox 60h Address (3 Cycle) Row Add. 1,2,3 A13 ~ A19 : Fixed “Low” A20 : Fixed “Low” A21 ~ A30 : Fixed “Low” R/B I/Ox 00h Address (5 Cycle) Col. Add 1,2 & Row Add. 1,2 ...
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R/B I/Ox 60h Address (3 Cycle) Row Add. 1,2,3 A13 ~ A19 : Fixed “Low” A20 : Fixed “Low” A21 ~ A30 : Fixed “Low” R/B I/Ox 00h Address (5 Cycle) Col. Add 1,2 & Row Add. 1,2 ...
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R/B I/Ox 60h Address (3 Cycle) Row Add. 1,2,3 A13 ~ A19 : Fixed “Low” A20 : Fixed “Low” A21 ~ A30 : Fixed “Low” R/B I/Ox 00h Address (5 Cycle) Col. Add 1,2 & Row Add. 1,2 ...
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R/B I/Ox 60h Address (3 Cycle) Row Add. 1,2,3 A13 ~ A19 : Fixed “Low” A20 : Fixed “Low” A21 ~ A30 : Fixed “Low” R/B I/Ox 00h Address (5 Cycle) Col. Add 1,2 & Row Add. 1,2 ...
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R/B Address (5 Cycles) I/Ox 85h Col. Add 1,2 & Row Add. 1,2,3 6 Destination Address A0 ~ A12 : Valid A13 ~ A19 : Fixed “Low” A20 A21 ~ A30 : Fixed “Low” R/B I/Ox 00h Address (5 Cycle) ...
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CLE CE WE ALE RE 90h I/O x Read ID Command Address 1 cycle Rev 0.0 / Jul. 2008 8 Gbit (1024 bit) NAND Flash tAR tREA D3h 00h ADh Maker Code Device Code Figure 26 : ...
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VCC 0V don’t care CE 1ms max 100us max Invalid ReadyBusy Figure 28 : Power on and Data Protection Timing Rev 0.0 / Jul. 2008 H27U8G8T2B Series 8 Gbit (1024 bit) NAND ...
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Rp Vcc R/B open drain output GND Device Rp value guidence Vcc (Max (min where IL is the sum of the input currnts of all devices tied to the R/B pin. Rp(max) is ...
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Figure 30 : Program Operation with CE don’t care Figure 31 : Read Operation with CE don’t care Rev 0.0 / Jul. 2008 Preliminary H27U8G8T2B Series 8 Gbit (1024 bit) NAND Flash 44 ...
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Bad Block Management Devices with bad blocks have the same quality level and the same AC and DC characteristics as devices where all the blocks are valid. A Bad Block does not affect the performance of valid blocks because it ...
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Bad Block Replacement Over the lifetime of the device additional Bad Blocks may develop. In this case the block has to be replaced by copying the data to a valid block. These additional Bad Blocks can be identified as attempts ...
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Write Protect Operation The Erase and Program Operations are automatically reset when WP goes Low (tWW = 100ns, min). The operations are enabled and disabled as follows (Figure 34~37) Figure 34 : Enable Programming Figure 36 : Enable Erasing Rev ...
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The Backward Compatibility (2KByte/page operation) 1. Page Program R/B Address & Data Input 80h I/O0~7 Col. Add 1,2 & Row Add. 1,2 2112 Byte Data A0 ~ A12 : Valid A13 ~ A19 : Fixed “Low” A20 : ...
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Copy back program with random data input R/B I/Ox R/B I/Ox Add. (5Cycles) 85h Col. Add 1,2 & Row Add. 1,2 2112 Byte Data Destination Address A0 ~ A12 : Valid A13 ~ A19 : Fixed ...
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Paired Page Address Information Paired Page Address Group A ooh 02h 06h 0Ah 0Eh 12h 16h 1Ah 1Eh 22h 26h 2Ah 2Eh 32h 36h 3Ah 3Eh 42h 46h 4Ah 4Eh 52h 56h 5Ah 5Eh 62h 66h 6Ah 6Eh 72h 76h ...
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Figure 38 : 48-TSOP1 - 48-lead Plastic Thin Small Outline 20mm, Package Outline Symbol alpha Table 21 : 48-TSOP1 - 48-lead Plastic Thin Small Outline ...
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MARKING INFORMATION - ...