ZL50012QCG1 Zarlink, ZL50012QCG1 Datasheet - Page 10

• Manufacturer Part Number: ZL50012QCG1
• Description: Switch Fabric 256 x 256 3.3V 160-Pin LQFP Tray
• Manufacturer: Zarlink

Specifications of ZL50012QCG1

• Package: 160LQFP
• Number Of Ports: 16
• Fabric Size: 256 x 256
• Switch Core: Non-Blocking
• Port Speed: 8.192|4.096|2.048 Mbps
• Operating Supply Voltage: 3.3 V

Pin Description (continued)
LQFP Pin
14, 15, 19
Number
24 - 28
30, 31
12
13
16
17
20
22
34
35
36
37
11
A6, A5, B6,
LBGA Ball
C9, C8, A8
Number
B5, C7
C4, A4
C10
B9
A9
D8
B8
A7
B7
A3
B4
B3
B2
ICONN2 - 3
NC1, NC2,
CLKBYPS
V
V
ICONN1
IC0 - 4
DD_APLL
Name
ss_APLL
CKo0
CKo1
FPo0
FPo1
SG1
TM1
TM2
NC3
Zarlink Semiconductor Inc.
APLL Test Control (3.3 V Input with internal pull-down): For
normal operation, this input MUST be low.
APLL Test Pin 1: For normal operation, this input MUST be
low.
APLL Test Pin 2: For normal operation, this input MUST be
low.
No Connection: These pins MUST be left unconnected.
Ground for the APLL Circuit.
Power Supply for the on-chip Analog Phase Lock Loop
(APLL) Circuit: +3.3 V
Internal Connection: In normal mode, this pin must be low.
Test Clock Input: For device testing only, in normal operation,
this input MUST be low.
Internal connection (3.3 V Tolerant Inputs with internal
pull-down):
In normal mode, these pins must be low.
Internal Connection: In normal mode, these pins must be low.
ST-BUS Frame Pulse Output 0 (5 V Tolerance Three-state
Output): ST-BUS frame pulse output which stays low for
244 ns or 122 ns at the output frame boundary. Its frequency is
8 KHz. The polarity of this signal can be changed using the
Internal Mode Selection register.
ST-BUS Clock Output 0 (5 V Tolerant Three-state Output):
A 4.094 MHz or 8.192 MHz clock output. The clock falling edge
defines the output frame boundary. The polarity of this signal
can be changed using the Internal Mode Selection register.
ST-BUS Frame Pulse Output 1 (5 V Tolerant Three-state
Output): ST-BUS frame pulse output which stays low for 61 ns
or 122 ns at the output frame boundary. Its frequency is 8 KHz.
The polarity of this signal can be changed using the Internal
Mode Selection register.
ST-BUS Clock Output 1 (5 V Tolerant Three-state Output):
A 16.384 MHz or 8.192 MHz clock output. The clock falling
edge defines the output frame boundary. The polarity of this
signal can be changed using the Internal Mode Selection
register.
ZL50012
13
Description
Data Sheet