ZL50012QCG1 Zarlink, ZL50012QCG1 Datasheet - Page 4

• Manufacturer Part Number: ZL50012QCG1
• Description: Switch Fabric 256 x 256 3.3V 160-Pin LQFP Tray
• Manufacturer: Zarlink

Specifications of ZL50012QCG1

• Package: 160LQFP
• Number Of Ports: 16
• Fabric Size: 256 x 256
• Switch Core: Non-Blocking
• Port Speed: 8.192|4.096|2.048 Mbps
• Operating Supply Voltage: 3.3 V

Figure 1 - ZL50012 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Figure 2 - 24 mm x 24 mm LQFP (JEDEC MS-026) Pinout Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 3 - 13 mm x 13 mm 144 Ball LBGA Pinout Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 4 - Input Timing when (CKIN2 to CKIN0 bits = 010) in the Control Register . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 5 - Input Timing when (CKIN2 to CKIN0 bits = 001) in the Control Register . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 6 - Input Timing when (CKIN2 to CKIN0 bits = 000) in the Control Register . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 7 - ST-BUS Input Timing for Various Input Data Rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 8 - FPo0 and CKo0 Output Timing when the CKFP0 bit = 0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 9 - FPo0 and CKo0 Output Timing when the CKFP0 bit = 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 10 - FPo1 and CKo1 Output Timing when the CKFP1 bit = 0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 11 - FPo1 and CKo1 Output Timing when the CKFP1 bit = 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 12 - FPo2 and CKo2 Output Timing when the CKFP2 bit = 0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 13 - FPo2 and CKo2 Output Timing when the CKFP2 bit = 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 14 - ST-BUS Output Timing for Various Output Data Rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 15 - Input Channel Delay Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 16 - Input Bit Delay Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 17 - Output Channel Delay Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 18 - Output Bit Delay Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 19 - Fractional Output Bit Advancement Timing Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 20 - Example: External High Impedance Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 21 - Data Throughput Delay when input and output channel delay are disabled for Input Ch0 switched to
Figure 22 - Data Throughput Delay when input channel delay is enabled and output channel delay is disabled for
Figure 23 - Data Throughput Delay when input channel delay is disabled and output channel delay is enabled for
Figure 24 - Data Throughput Delay when input and output channel delay are enabled for Input Ch0 switched to
Figure 25 - Frame Pulse Input and Clock Input Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Figure 26 - Frame Boundary Timing with Input Clock (cycle-to-cycle) Variation . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Figure 27 - Frame Boundary Timing with Input Frame Pulse (cycle-to-cycle) Variation . . . . . . . . . . . . . . . . . . . . 57
Figure 28 - Input and Output Frame Boundary Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Figure 29 - FPo0 and CKo0 Timing Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Figure 30 - FPo1 and CKo1 Timing Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Figure 31 - FPo2 and CKo2 Timing Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Figure 32 - ST-BUS Inputs (STi0 - 15) Timing Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Figure 33 - ST-BUS Outputs (STo0 - 15) Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Figure 34 - Serial Output and External Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Figure 35 - Output Driver Enable (ODE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Figure 36 - Motorola Non-Multiplexed Bus Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Figure 37 - JTAG Test Port Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Figure 38 - Reset Pin Timing Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Output Ch0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Input Ch0 switched to Output Ch0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Input Ch0 switch to Output Ch0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Output Ch0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Zarlink Semiconductor Inc.
List of Figures
ZL50012
4
Data Sheet