71V124SA12PHG8 Integrated Device Technology (Idt), 71V124SA12PHG8 Datasheet

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71V124SA12PHG8

Manufacturer Part Number
71V124SA12PHG8
Description
SRAM Chip Async Single 3.3V 1M-Bit 128K x 8 12ns 32-Pin TSOP-II T/R
Manufacturer
Integrated Device Technology (Idt)
Datasheet

Specifications of 71V124SA12PHG8

Package
32TSOP-II
Timing Type
Asynchronous
Density
1 Mb
Typical Operating Supply Voltage
3.3 V
Address Bus Width
17 Bit
Number Of I/o Lines
8 Bit
Number Of Ports
1
Number Of Words
128K
Features
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Functional Block Diagram
©2004- Integrated Device Technology, Inc.
128K x 8 advanced high-speed CMOS static RAM
JEDEC revolutionary pinout (center power/GND) for
reduced noise
Equal access and cycle times
– Commercial: 10/12/15/20ns
– Industrial: 10/12/15/20ns
One Chip Select plus one Output Enable pin
Inputs and outputs are LVTTL-compatible
Single 3.3V supply
Low power consumption via chip deselect
Available in a 32-pin 300- and 400-mil Plastic SOJ, and
32-pin Type II TSOP packages.
I/O
0
- I/O
A
A
16
7
0
WE
OE
CS
8
ADDRESS
DECODER
8
3.3V CMOS Static RAM
1 Meg (128K x 8-Bit)
Center Power &
Ground Pinout
CONTROL
LOGIC
1
Description
as 128K x 8. It is fabricated using IDT’s high-performance, high-reliability
CMOS technology. This state-of-the-art technology, combined with inno-
vative circuit design techniques, provides a cost-effective solution for high-
speed memory needs. The JEDEC center power/GND pinout reduces
noise generation and improves system performance.
5ns, with address access times as fast as 9ns available. All bidirec-
tional inputs and outputs of the IDT71V124 are LVTTL-compatible and
operation is from a single 3.3V supply. Fully static asynchronous
circuitry is used; no clocks or refreshes are required for operation.
The IDT71V124 is a 1,048,576-bit high-speed static RAM organized
The IDT71V124 has an output enable pin which operates as fast as
MEMORY ARRAY
I/O CONTROL
1,048,576-BIT
3873 drw 01
OCTOBER 2008
IDT71V124SA
8
.
DSC-3873/08

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71V124SA12PHG8 Summary of contents

Page 1

Features ◆ ◆ ◆ ◆ ◆ 128K x 8 advanced high-speed CMOS static RAM ◆ ◆ ◆ ◆ ◆ JEDEC revolutionary pinout (center power/GND) for reduced noise ◆ ◆ ◆ ◆ ◆ Equal access and cycle times – Commercial: 10/12/15/20ns ...

Page 2

IDT71V124SA, 3.3V CMOS Static RAM 1 Meg (128K x 8-Bit) Center Power & Ground Pinout Pin Configuration I SO32-2 7 I/O 1 SO32-3 V ...

Page 3

IDT71V124SA, 3.3V CMOS Static RAM 1 Meg (128K x 8-Bit) Center Power & Ground Pinout DC Electrical Characteristics (V = Min. to Max 0.2V Symbol Parameter I Dynamic Operating Current CC CS < ...

Page 4

IDT71V124SA, 3.3V CMOS Static RAM 1 Meg (128K x 8-Bit) Center Power & Ground Pinout AC Electrical Characteristics (V = Min. to Max., Commercial and Industrial Temperature Ranges) DD Symbol Parameter READ CYCLE t Read Cycle Time RC t Address ...

Page 5

IDT71V124SA, 3.3V CMOS Static RAM 1 Meg (128K x 8-Bit) Center Power & Ground Pinout Timing Waveform of Read Cycle No. 1 ADDRESS OE CS HIGH IMPEDANCE DATA OUT Timing Waveform of Read Cycle No. 2 ADDRESS PREVIOUS DATA DATA ...

Page 6

IDT71V124SA, 3.3V CMOS Static RAM 1 Meg (128K x 8-Bit) Center Power & Ground Pinout Timing Waveform of Write Cycle No. 1 (WE Controlled Timing) ADDRESS (3) DATA OUT DATA IN Timing Waveform of Write Cycle ...

Page 7

IDT71V124SA, 3.3V CMOS Static RAM 1 Meg (128K x 8-Bit) Center Power & Ground Pinout Ordering Information 71V124 SA XX Device Power Speed Type Process/ Package Temperature Range 7 6.42 Commercial and Industrial Temperature Ranges Blank Commercial ...

Page 8

IDT71V124SA, 3.3V CMOS Static RAM 1 Meg (128K x 8-Bit), Center Power & Ground Pinout Datasheet Document History 11/22/99 Updated to new format Pg. 1–4, 7 Added Industrial Temperature range offerings Pg. 2 Added Recommended Operating Temperature and Supply Voltage ...

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