71V124SA12PHG8 Integrated Device Technology (Idt), 71V124SA12PHG8 Datasheet - Page 5

• Manufacturer Part Number: 71V124SA12PHG8
• Description: SRAM Chip Async Single 3.3V 1M-Bit 128K x 8 12ns 32-Pin TSOP-II T/R
• Manufacturer: Integrated Device Technology (Idt)

Specifications of 71V124SA12PHG8

• Package: 32TSOP-II
• Timing Type: Asynchronous
• Density: 1 Mb
• Typical Operating Supply Voltage: 3.3 V
• Address Bus Width: 17 Bit
• Number Of I/o Lines: 8 Bit
• Number Of Ports: 1
• Number Of Words: 128K

Timing Waveform of Read Cycle No. 1
Timing Waveform of Read Cycle No. 2
NOTES:
1. WE is HIGH for Read Cycle.
2. Device is continuously selected, CS is LOW.
3. Address must be valid prior to or coincident with the later of CS transition LOW; otherwise t
4. OE is LOW.
5. Transition is measured ±200mV from steady state.
ADDRESS
IDT71V124SA, 3.3V CMOS Static RAM
1 Meg (128K x 8-Bit) Center Power & Ground Pinout
ADDRESS
DATA
DATA
OUT
OUT
OE
CS
PREVIOUS DATA
HIGH IMPEDANCE
OUT
VALID
t
OH
t
CLZ
t
OLZ
(5)
(5)
t
t
AA
AA
t
ACS
(3)
t
t
RC
RC
6.42
t
OE
5
(1)
(1, 2, 4)
AA
is the limiting parameter.
Commercial and Industrial Temperature Ranges
DATA
DATA
t
CHZ
OUT
(5)
OUT
VALID
t
VALID
OHZ
t
OH
(5)
3873 drw 05
3873 drw 06
.
.