MT8985AL Zarlink, MT8985AL Datasheet
MT8985AL
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MT8985AL Summary of contents
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... MT8985AE MT8985AP MT8985AL MT8985APR MT8985AP1 MT8985APR1 44 Pin PLCC* MT8985AE1 MT8985AL1 Switch (DX pin compatible with the MT8980D and retains all of the MT8980D's functionality. This VLSI device is designed for switching PCM-encoded voice or data, under microprocessor control, in digital exchanges, PBXs environment. It provides simultaneous connections for up to 256 64 kb/s channels ...
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... STo4 STi6 8 33 STo5 9 32 STo6 STi7 VDD 10 31 STo7 11 30 F0i VSS C4i R PIN PLASTIC DIP Figure 2 - Pin Connections 2 Zarlink Semiconductor Inc. Data Sheet Change 1 33 STo3 2 32 STo4 3 31 STo5 4 30 STo6 5 29 STo7 6 28 VSS PIN QFP ...
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... CSTo Control ST-BUS Output (Output). This output is a 2.048 Mb/s line which contains 256 bits per frame. The level of each bit is controlled by the contents of the CSTo bit in the Connect Memory high locations. 6, 18, 12, Connection. 28, 34 MT8985 Description 3 Zarlink Semiconductor Inc. Data Sheet ...
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... By using Zarlink Message mode capability, the microprocessor can access input and output time slots on a per channel basis to control devices such as the Zarlink MT8972, ISDN Transceivers and T1/CEPT trunk interfaces through the ST-BUS interface ...
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... Any switching configuration that provides three or more timeslots between input and output channels, will have a throughput delay equal to the difference between the output and input channels; i.e., the throughput delay will be less than one frame. Table 1 shows the possible delays for the MT8985 device in Variable Delay mode: MT8985 5 Zarlink Semiconductor Inc. Data Sheet ...
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... Microprocessor Port The MT8985 microprocessor port has pin compatibility with Zarlink MT8980 Digital Switch device providing a non- multiplexed bus architecture. The parallel port consists bit parallel data bus (D0-D7), six address input lines (A0-A5) and four control lines (CS, DS, R/W and DTA). This parallel microport allows the access to the Control registers, Connection Memory High, Connection Memory Low and the Data Memory ...
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... Channel 1 • • • • • • • • • • • • • • • • • • • • • • • • • Channel 31 Figure 3 - Address Memory Map 7 Zarlink Semiconductor Inc. Data Sheet • • • • • ...
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... MT8985 ST-BUS outputs are tied together to form matrices, as these outputs may conflict. The ODE pin should be held low on power up to keep all outputs in the high impedance condition. MT8985 MS1 MS0 STA2 DESCRIPTION Figure 4 - Control Register Bits 8 Zarlink Semiconductor Inc. Data Sheet 1 0 STA1 STA0 ...
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... ODE signal high to relinquish high impedance state control to the CMH MT8985 V DESCRIPTION Figure 5 - Connection Memory High Bits SAB1 SAB0 CAB4 CAB3 CAB2 DESCRIPTION Figure 6 - Connection Memory Low Bits 9 Zarlink Semiconductor Inc. Data Sheet 1 0 CSTo CAB1 CAB0 0s. b ...
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... MT8930/31 S/U MT8910 MT8972 Figure 7 - Typical Exchange, PBX or Multiplexer Configuration MT8985 To other lines Layers 2 & 3 Entity ST-BUS To other lines ROUTING MATRIX MT8985’s MT8940/ MT8941 µC Primary Rate Card 10 Zarlink Semiconductor Inc. Data Sheet ST-BUS ST-BUS T1/E1 Link MH89760/ MH89790 MT8920 ...
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... Another application of the MT8985 in an MVIP environment is to build an ISDN S-interface card (Figure 11). In this card, 7 pairs of ST-BUS streams are connected to the MVIP interface while the remaining pair is reserved for the interconnection of Zarlink MT8930 (SNIC), MT8992 (H-PHONE) and the MVIP interface. MT8985 ...
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... MH89760B/790B • • Local T1/E1 Link MT8972B ST-BUS MH89760B or MH89790B ANALOG MT8985s (x4) Server 2 MVIP BUS Figure 8b - Implementation of an Isochronous Network Using Zarlink Components MT8985 ISDN S-Interface • • • • • MVIP BUS MT8985 MT8985 MT8985s (x4) MT8985 MT8985 HDLC • • ...
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... Input Streams From MVIP 8 Input On-Board ST-BUS Streams Figure 9 - 512-Channel Switch Array MT8985 MT8985 #1 CSTo MVIP Direction MT8985 #2 CSTo MVIP Enable MT8985 #3 MT8985 #4 13 Zarlink Semiconductor Inc. Data Sheet 8 Output Streams to MVIP 8 Output On-Board ST-BUS Streams ...
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... MT8985 T1/E1 MH89760B SWITCH MT8985 or MH89790B HDLC MT8952B ANALOG D-PHONE MT8992/93 PC INTERFACE Figure 10 - Dual T1/E1 Card Functional Block Diagram Zarlink Semiconductor Inc. MT8985 MVIP HEADER MVIP STi0-7 512 Channel SWITCH Switch Matrix MT8985 SWITCH MT8985 DPLL MT8941 14 Data Sheet FDL HDLC ...
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... MT8985 MVIP HEADER MVIP STo1-7 STi7-1 SWITCH MT8985 STi0 S INTERFACE HDLC MT8930B DIGITAL PHONE HDLC MT8992/93 PC INTERFACE Figure 11 - S-Access Card Functional Block Diagram 15 Zarlink Semiconductor Inc. MVIP STi1-7 STo7-1 MATRIX STo0 DPLL MT8941 DTMF RECEIVER MT8870 Data Sheet ...
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... unless otherwise stated. SS ‡ Sym. Min. Typ. Max 2 0 100 2 0 Zarlink Semiconductor Inc. Data Sheet Min. Max. Units -0 -0 -0 °C -65 +150 unless otherwise stated. Units Test Conditions ° Units Test Conditions mA Outputs unloaded between V and Sourcing ...
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... STiH t 200 244 300 C4i t 85 122 150 122 150 ± =5V 5%, V =0V Zarlink Semiconductor Inc. Data Sheet S1 is open circuit except when testing output levels or high impedance states switched when testing output SS levels or high impedance states. Units Test Conditions =150 ° ...
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... 244 WFH t 10 F0iS t 20 F0iH t 45 DAA t 20 STiS t 20 STiH ± =5V 5%, V =0V Zarlink Semiconductor Inc. Data Sheet Ch. 0 Ch. 0 Bit 6 Bit 5 Ch. 0 Ch. 0 Bit 6 Bit 5 Max. Units Test Conditions 300 ns 150 ns ns 190 ns 190 ns 100 ns C =150 pF ...
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... STiS t DAA Figure 14 - GCI Timing ‡ Sym. Min. Typ. Max. t 100 SAZ t 100 SZA t OED t 0 XCD , with timing corrected to cancel time taken to discharge Zarlink Semiconductor Inc. Data Sheet bit 2 bit 3 t C4i Units Test Conditions KΩ*, C =150 =150 KΩ*, C =150 pF ...
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... C4i 0.8V STo0 2.4V to STo7 0.4V t 2.4V STo0 * to STo7 0.4V 2.4V CSTo 0.4V Figure 15 - Serial Outputs and External Control 2.0V ODE 0.8V STo0 2. STo7 0. OED OED Figure 16 - Output Driver Enable 20 Zarlink Semiconductor Inc. Data Sheet (GCI) (ST-BUS) * SAZ t SZA t XCD * ...
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... ADH t 10 DDR DHR t 20 DSW t 122 SWD t 8 DHW t AKD 560 1220 300/370 730/800 155 110 AKH , with timing corrected to cancel time taken to discharge Zarlink Semiconductor Inc. Data Sheet Units Test Conditions =150 KΩ*, L C =150 =150 KΩ*, L C =150 pF L ...
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... D0-D7 READ 0.8V 2.0V D0-D7 WRITE 0.8V 2.0V DTA 0.8V Figure 17 - Motorola Non-Multiplexed Bus Timing MT8985 t CSS t RWS t ADS VALID DATA t t SWD DSW VALID DATA t DDR t AKD 22 Zarlink Semiconductor Inc. Data Sheet t CSH t RWH t ADH t DHR t DHW t AKH ...
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... Zarlink, or non-Zarlink furnished goods or services may infringe patents or other intellectual property rights owned by Zarlink. This publication is issued to provide information only and (unless agreed by Zarlink in writing) may not be used, applied or reproduced for any purpose nor form part of any order or contract nor to be regarded as a representation relating to the products or services concerned ...