MT8985AL Zarlink, MT8985AL Datasheet - Page 7

• Manufacturer Part Number: MT8985AL
• Description: Switch Fabric 256 x 256 16.384Mbps 5V 44-Pin MQFP Tray
• Manufacturer: Zarlink

Specifications of MT8985AL

• Package: 44MQFP
• Number Of Ports: 8
• Fabric Size: 256 x 256
• Switching Bandwidth: 16.384 Mbps
• Switch Core: Non-Blocking
• Port Speed: 2.048 Mbps
• Operating Supply Voltage: 5 V

Software Control
The address lines on the microprocessor interface give access to the MT8985 internal registers and memories. If
the A5,A1,A0 address line inputs are LOW, then the MT8985 Internal Control Register is addressed (see Figure 3).
If A5 input line is HIGH, then the remaining address input lines are used to select Memory subsections of 32
locations corresponding to the number of channels per input or output stream. As explained in the Control register
description, the address input lines and the Stream Address bits (STA) of the Control register give the user the
capability of selecting all positions of the MT8985 Data and Connect memories.
The data in the Control register consists of Split memory and Message mode bits, Memory select and Stream
Address bits (see Figure 4). The memory select bits allow the Connect Memory HIGH or LOW or the Data Memory
to be chosen, and the Stream Address bits define an internal memory subsections corresponding to input or output
ST-BUS streams. Bit 7 (Split Memory) of the Control register allows split memory operation whereby reads are from
the Data memory and writes are to the Connect Memory LOW.
The Message Enable bit (bit 6) places every output channel on every output stream in message mode; i.e., the
contents of the Connect Memory LOW (CML) are output on the ST-BUS output streams once every frame unless
the ODE input pin is LOW. If ME bit is HIGH, then the MT8985 behaves as if bits 2 (Message Channel) and 0
(Output Enable) of every Connect Memory HIGH (CMH) locations were set to HIGH, regardless of the actual value.
If ME bit is LOW, then bit 2 and 0 of each Connect Memory HIGH location operates normally. In this case, if bit 2 of
the CMH is HIGH, the associated ST-BUS output channel is in Message mode. If bit 2 of the CMH is LOW, then the
contents of the CML define the source information (stream and channel) of the time slot that is to be switched to an
output.
If the ODE input pin is LOW, then all serial outputs are high-impedance. If ODE is HIGH, then bit 0 (Output Enable)
of the CMH location enables (if HIGH) or disables (if LOW) the output drivers for the corresponding individual ST-
BUS output stream and channel.
The contents of bit 1 (CSTo) of each Connection Memory High location (see Figure 5) is output on CSTo pin once
every frame. The CSTo pin is a 2048 Mbit/s output which carries 256 bits. If CSTo bit is set HIGH, the
corresponding bit on CSTo output is transmitted in HIGH. If CSTo bit is LOW, the corresponding bit on the CSTo
output is transmitted in LOW. The contents of the 256 CSTo bits of the CMH are transmitted sequentially on to the
CSTo output pin and are synchronous to the ST-BUS streams. To allow for delay in any external control circuitry the
contents of the CSTo bit is output one channel before the corresponding channel on the ST-BUS streams. For
example, the contents of CSTo bit in position 0 (ST0, CH0) of the CMH, is transmitted synchronously with ST-BUS
channel 31, bit 7. The contents of CSTo bit in position 32 (ST1, CH0) of the CMH is transmitted during ST-BUS
channel 31 bit 6. Bit V/C (Variable/Constant Delay) on the Connect Memory High locations allow per-channel
selection between Variable and Constant throughput delay capabilities.
Note: "x" Don’t care
A5
0
1
1
1
1
1
1
1
1
A4
0
0
0
1
•
•
•
•
•
Figure 3 - Address Memory Map
A3
0
0
0
1
•
•
•
•
•
Zarlink Semiconductor Inc.
A2
0
0
0
1
•
•
•
•
•
MT8985
A1
0
0
0
1
•
•
•
•
•
7
A0
0
0
1
1
•
•
•
•
•
Control Register
LOCATION
Channel 31
Channel 0
Channel 1
•
•
•
•
•
Data Sheet