MT90840AP Zarlink, MT90840AP Datasheet - Page 13

• Manufacturer Part Number: MT90840AP
• Description: Switch Fabric 512 x 2430/512 x 512/2.373K x 2.373K 5V 84-Pin PLCC Tube
• Manufacturer: Zarlink

Specifications of MT90840AP

• Package: 84PLCC
• Number Of Ports: 16
• Fabric Size: 512 x 2430|512 x 512|2.373K x 2.373K
• Switch Core: Non-Blocking
• Port Speed: 8.192|4.096|2.048 Mbps
• Operating Supply Voltage: 5 V

Serial Port Clock Signals
Depending on the Timing Mode selected, the serial port clock is either an input, or an output derived from a
reference clock. In modes where the serial clock is derived by the MT90840 from a reference clock, the serial port
clock output appears at SPCKo. The reference clock is either PCKR (if INTCLK is high), or one of C4/8R1 or
C4/8R2. The C4/8R bit of the Timing Mode Register is used to select which of C4/8R1 or C4/8R2 will be the clock
source or reference pin. Switching between clock sources during device operation will cause temporary TDM data
errors.
Internal 4.096 MHz Clock Generator
For TM2 applications running at 19.44 or 16.384 MHz rates on the parallel port, an internal divider can be used to
generate a 4.096 MHz clock from the PCKR clock input. The internal divider can not be used in applications where
the parallel port operates at 6.480 Mbyte/s rates. The INTCLK bit in the TIM Register enables the internal divider,
and the SPCKo output (and internal 4.096 MHz clocks) are driven by the clock divided-down from PCKR. At
16.384 MHz, this is a simple divide-by-4, and the SPCKo output jitter will depend on the PCKR input jitter. At
19.44 MHz, the SPCKo output jitter will be larger as the divider switches between rising and falling edges of PCKR.
The serial port timing and F0o frame pulse are tightly slaved to PPFRi when INTCLK is set high.
Serial Frame Pulse
In TM1, the MT90840 receives the frame reference (F0i) from an external source, and the MT90840 senses the
polarity of the frame pulse and adapts the device timing to the appropriate (ST-BUS or GCI) format.
In TM2 and TM3, the MT90840 outputs the serial port frame pulse (F0o). Positive (GCI) or negative (ST-BUS)
frame pulse formats, and the associated clock polarity, can be selected for the F0o signal by programming the
SPFP bit in the GPM Register. This flexibility allows the MT90840 to be employed with different serial bus formats.
In applications which require a large number of serial channels in TM2, it is possible to operate multiple MT90840s
in parallel using the SFDI control bit (in the TIM register). To allow the MT90840s to synchronize their internal
timing, all of the MT90840s are connected to the same C4/8 reference source, and one MT90840 in normal TM2
(SFDI set low) supplies F0 to one or more MT90840s in TM2 with SFDI set high. With SFDI set high, F0 becomes
an input, and this allows the MT90840 driving F0 to control the timing of one or more other MT90840s. If the internal
4.096 MHz clock divider is used (INTCLK high) it is not necessary to use the SFDI control, as the serial port timing
and F0o frame pulse of each parallel MT90840 will be tightly slaved to PPFRi when INTCLK is set high.
Should the input framing at F0i cease while the C4/8 clock continues to run, the MT90840 will continue to function
as if the frame pulse was asserted after the normal number of clock cycles (free run). If F0i re-commences the
MT90840 will immediately sync to F0i, but changes in the F0i interval will temporarily disrupt the TDM data streams.
If the F0i input is held asserted, the serial I/O will “lock up” and operation will be disrupted.
Parallel Data Port
The MT90840 parallel port is composed of an 8-bit wide Parallel Data Output Port (PDo0-7), a 4-bit wide Control
output port (CTo0-3), an 8-bit wide Parallel Data Input Port (PDi0-7), a Receive Frame sync signal (PPFRi) and a
Transmit Frame sync signal (PPFT), and Transmit (PCKT) and Receive (PCKR) Clocks.
The Parallel Port Rates are controlled by the PPS bits in the IMS register, and are:
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The user can further specify the features of the parallel TDM port, including:
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19.44 Mbyte/s (2430 channels),
16.384 Mbyte/s (2048 channels), and
6.48 Mbyte/s (810 channels).
the edge of the parallel port clock used to transmit data and PPFTo (see TCP bit in the TIM register),
the polarity of the Parallel Port Frame Transmit pulse PPFT (see PPFP bit in the GPM register),
Zarlink Semiconductor Inc.
MT90840
13
Data Sheet