MT90840AP Zarlink, MT90840AP Datasheet - Page 37

• Manufacturer Part Number: MT90840AP
• Description: Switch Fabric 512 x 2430/512 x 512/2.373K x 2.373K 5V 84-Pin PLCC Tube
• Manufacturer: Zarlink

Specifications of MT90840AP

• Package: 84PLCC
• Number Of Ports: 16
• Fabric Size: 512 x 2430|512 x 512|2.373K x 2.373K
• Switch Core: Non-Blocking
• Port Speed: 8.192|4.096|2.048 Mbps
• Operating Supply Voltage: 5 V

General Purpose Mode Register (GPM) - READ/WRITE
BPD7-4
PPFP
DIN
SPFP
BPE
Note
:
the Memory Block-Programming feature is activated. When BPE is set HIGH, the contents of bits BPD7-4 are loaded into the
four most significant bits of TPCM-High or RPCM-High, and the four least significant bits of TPCM-High or RPCM-High are
zeroed.
boundaries at the Parallel Port output will occur when PPFT pulse signal is HIGH. If PPFP is set LOW, the PPFT output will
indicate frame boundaries with a LOW active pulse. The transmit edge for the generation of PPFT, as well as PDo and CTo, is
determined by TCP in the TIM Register.
serial port clock. It can be set HIGH by the CPU after the serial and parallel port rates are written in the IMS Register, and the
input clocks are stable. If the MT90840 internal divider is used (INTCLK bit = HIGH), or if TM4 or TM3 is selected, this bit is
not used. This bit is automatically returned low after 8 frames, and clears all interrupt source bits in the ALS register as long as
it is HIGH. The Connect Memories should not be programmed while DIN is asserted.
SPCKo. If SPFP is HIGH, F0o is set as a positive pulse with GCI timing. If SPFP is LOW, F0o is set as a negative pulse with
ST-BUS timing. In TM2 with SFDI set HIGH, this bit specifies the expected F0i input polarity. In TM1, the F0i input polarity is
automatically detected, and this bit is ignored. See the interface timing specifications.
in the Control Register are set to select the memory to be programmed. The BPE and BPD7-4 bits in this register must be
defined in the same write operation. Once BPE is set HIGH, the user should wait at least 250 µs and then check BPE = LOW to
see that the operation completed successfully. This bit can also be written low to force the end of the block-program operation.
function should not be used simultaneously.
Block-Programming Data bits 7-4. These bits carry the value to be loaded into the TPCM-High or RPCM-High memory when
Parallel Port Frame pulse Polarity. Used to program the polarity of the PPFT frame pulse. If PPFP is set HIGH, the frame
Device Initialization. This bit is used in TM1 and TM2 to center the phase relation between the parallel port clocks and the
Serial Port Framing Polarity. In TM2 and TM3 this bit defines the format of the serial port frame pulse F0o, and the clock
Block-Programming Enable. This bit activates the memory block-programming feature. It can be set high after the SEL0-2 bits
The CPU must maintain the required settings of the PPFP and SPFP bits when BPE is written. The DIN function and the BPE
BPD7
7
BPD6
6
BPD5
5
BPD4
4
Zarlink Semiconductor Inc.
PPFP
3
MT90840
37
DIN
2
SPFP
1
BPE
0
Data Sheet