PI7C9X111SLBFDE Pericom Semiconductor, PI7C9X111SLBFDE Datasheet - Page 30

• Manufacturer Part Number: PI7C9X111SLBFDE
• Manufacturer: Pericom Semiconductor

Specifications of PI7C9X111SLBFDE

• Lead Free Status / Rohs Status: Compliant

6.3.18 MEMORY BASE REGISTER – OFFSET 20h
6.3.19 MEMORY LIMIT REGISTER – OFFSET 20h
6.3.20 PREFETCHABLE MEMORY BASE REGISTER – OFFSET 24h
Pericom Semiconductor - Confidential
BIT
26:25
27
28
29
30
31
BIT
3:0
15:4
BIT
19:16
31:20
BIT
FUNCTION
DEVSEL_L Timing
(medium decoding)
Signaled Target Abort
Received Target Abort
Received Master Abort
Received System Error
Detected Parity Error
FUNCTION
Reserved
Memory Base
FUNCTION
Reserved
Memory Limit
FUNCTION
TYPE
TYPE
TYPE
TYPE
RWC
RWC
RWC
RWC
RWC
RW
RW
RO
RO
RO
Page 30 of 78
DESCRIPTION
These bits apply to forward bridge only.
01: medium DEVSEL_L decoding
Reset to 01 when forward mode or 00 when reverse mode.
FORWARD BRIDGE –
Bit is set when PI7C9X111SL signals target abort
REVERSE BRIDGE –
Bit is set when PI7C9X111SL completes a request using completer abort
completion status
Reset to 0
FORWARD BRIDGE –
Bit is set when PI7C9X111SL detects target abort on the secondary interface
REVERSE BRIDGE –
Bit is set when PI7C9X111SL receives a completion with completer abort
completion status on the secondary interface
Reset to 0
FORWARD BRIDGE –
Bit is set when PI7C9X111SL detects master abort on the secondary interface
REVERSE BRIDGE –
Bit is set when PI7C9X111SL receives a completion with unsupported
request completion status on the primary interface
Reset to 0
FORWARD BRIDGE –
Bit is set when PI7C9X111SL detects SERR_L assertion on the secondary
interface
REVERSE BRIDGE –
Bit is set when PI7C9X111SL receives an ERR_FATAL or
ERR_NON_FATAL message on the secondary interface
Reset to 0
FORWARD BRIDGE –
Bit is set when PI7C9X111SL detects address or data parity error
REVERSE BRIDGE –
Bit is set when PI7C9X111SL detects poisoned TLP on secondary interface
Reset to 0
DESCRIPTION
Reset to 0000
Memory Base (80000000h)
Reset to 800h
DESCRIPTION
Reset to 0000
Memory Limit (000FFFFFh)
Reset to 000h
DESCRIPTION
Feb, 2010, Revision 1.5
PCIe-to-PCI Reversible Bridge
PI7C9X111SL