PI7C9X111SLBFDE Pericom Semiconductor, PI7C9X111SLBFDE Datasheet - Page 55

• Manufacturer Part Number: PI7C9X111SLBFDE
• Manufacturer: Pericom Semiconductor

Specifications of PI7C9X111SLBFDE

• Lead Free Status / Rohs Status: Compliant

6.3.88 L0 ENTER L1 WAITING PERIOD COUNTER – OFFSET D4h
6.3.89 CAPABILITY ID REGISTER – OFFSET D8h
6.3.90 NEXT POINTER REGISTER – OFFSET D8h
6.3.91 VPD REGISTER – OFFSET D8h
6.3.92 VPD DATA REGISTER – OFFSET DCh
Pericom Semiconductor - Confidential
BIT
31:24
BIT
7:0
BIT
15:8
BIT
17:16
23:18
30:24
31
BIT
31:0
FUNCTION
L0 enter L1 waiting period
counter
FUNCTION
Capability ID for VPD
Register
FUNCTION
Next Pointer
FUNCTION
Reserved
VPD Address for
Read/Write Cycle
Reserved
VPD Operation
FUNCTION
VPD Data
TYPE
TYPE
TYPE
TYPE
TYPE
RW
RW
RW
RW
RO
RO
RO
RO
Page 55 of 78
DESCRIPTION
L0 enter L1 waiting period counter
Reset to 00h
DESCRIPTION
Reset to 03h
DESCRIPTION
Next pointer (F0h, points to MSI capabilities)
Reset to F0h
DESCRIPTION
Reset to 0
Reset to 0
Reset to 0
0: Generate a read cycle from the EEPROM at the VPD address specified in
bits [7:2] of offset D8h. This bit remains at ‘0’ until EEPROM cycle is
finished, after which the bit is then set to ‘1’. Data for reads is available at
register ECh.
1: Generate a write cycle to the EEPROM at the VPD address specified in
bits [7:2] of offset D8h. This bit remains at ‘1’ until EEPROM cycle is
finished, after which it is then cleared to ‘0’.
Reset to 0
DESCRIPTION
VPD Data (EEPROM data [address + 0x40])
The least significant byte of this register corresponds to the byte of VPD at
the address specified by the VPD address register. The data read form or
written to this register uses the normal PCI byte transfer capabilities.
Reset to 0
=d0: 128ms
=d1: 129ms
=d127: 256ms
=d128: 0ms
=d129: 1ms
=d255: 127ms
.
.
.
.
Feb, 2010, Revision 1.5
PCIe-to-PCI Reversible Bridge
PI7C9X111SL