PI7C9X111SLBFDE Pericom Semiconductor, PI7C9X111SLBFDE Datasheet - Page 72

• Manufacturer Part Number: PI7C9X111SLBFDE
• Manufacturer: Pericom Semiconductor

Specifications of PI7C9X111SLBFDE

• Lead Free Status / Rohs Status: Compliant

13
13.1 INSTRUCTION REGISTER
13.2 BYPASS REGISTER
Upon receiving reset (cold, warm, hot, or DL_DOWN) on PCIe interface, PI7C9X111SL will generate PCI reset
(RESET_L) to the downstream devices on the PCI bus in forward bridge mode. The PCI reset de-assertion follows
the de-assertion of the reset received from PCIe interface. The reset bit of Bridge Control Register may be set
depending on the application. PI7C9X111SL will tolerant to receive and process SKIP order-sets at an average
interval between 1180 to 1538 Symbol Times. PI7C9X111SL does not keep PCI reset active when VD33 power is
off even though VAUX (3.3v) is supported. It is recommended to add a weak pull-down resistor on its application
board to ensure PCI reset is low when VD33 power is off (see section 7.3.2 of PCI Bus Power management
Specification Revision 1.1).
In reverse bridge mode, PI7C9X111SL generates fundamental reset (PERST_L) and then 1024 TS1 order-sets with
reset bit set when PCI reset (RESET_L) is asserted to PI7C9X111SL. PI7C9X111SL has scheduling skip order-set
for insertion at an interval between 1180 and 1538 Symbol Times.
PI7C9X111SL transmits one Electrical Idle order-set and enters to Electrical Idle.
An IEEE 1149.1 compatible Test Access Port (TAP) controller and associated TAP pins are provided to support
boundary scan in PI7C9X111SL for board-level continuity test and diagnostics. The TAP pins assigned are TCK,
TDI, TDO, TMS and TRST_L. All digital input, output, input/output pins are tested except TAP pins.
The IEEE 1149.1 Test Logic consists of a TAP controller, an instruction register, and a group of test data registers
including Bypass and Boundary Scan registers. The TAP controller is a synchronous 16-state machine driven by the
Test Clock (TCK) and the Test Mode Select (TMS) pins. An independent power on reset circuit is provided to
ensure the machine is in TEST_LOGIC_RESET state at power-up. The JTAG signal lines are not active when the
PCI resource is operating PCI bus cycles.
PI7C9X111SL implements a 5-bit Instruction register to control the operation of the JTAG logic. The defined
instruction codes are shown in Table 14-1. Those bit combinations that are not listed are equivalent to the BYPASS
(11111) instruction:
Table 13-1 Instruction register codes
Pericom Semiconductor - Confidential
IEEE 1149.1 COMPATIBLE JTAG CONTROLLER
Instruction
EXTEST
SAMPLE
HIGHZ
CLAMP
IDCODE
BYPASS
INT_SCAN
MEM_BIST
Operation Code (binary)
00000
00001
00101
00100
01100
11111
00010
01010
Register Selected
Boundary Scan
Boundary Scan
Bypass
Bypass
Device ID
Bypass
Internal Scan
Memory BIST
Page 72 of 78
Operation
Drives / receives off-chip test data
Samples inputs / pre-loads outputs
Tri-states output and I/O pins except TDO pin
Drives pins from boundary-scan register and selects Bypass register
for shifts
Accesses the Device ID register, to read manufacturer ID, part
number, and version number
Selected Bypass Register
Scan test
Memory BIST test
Feb, 2010, Revision 1.5
PCIe-to-PCI Reversible Bridge
PI7C9X111SL