PIC18F4585-H/PT Microchip Technology, PIC18F4585-H/PT Datasheet - Page 40

• Manufacturer Part Number: PIC18F4585-H/PT
• Description: IC MCU 8BIT 48KB FLASH 44TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F4585-H/PT

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: CAN, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 36
• Program Memory Size: 48KB (24K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 3.25K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 11x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 150°C
• Package / Case: 44-TQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC18F2585/2680/4585/4680
3.4.1
This mode is unique among the three Low-Power Idle
modes, in that it does not disable the primary device
clock. For timing sensitive applications, this allows for
the fastest resumption of device operation with its more
accurate primary clock source, since the clock source
does not have to “warm up” or transition from another
oscillator.
PRI_IDLE mode is entered from PRI_RUN mode by
setting the IDLEN bit and executing a SLEEP instruc-
tion. If the device is in another Run mode, set IDLEN
first, then clear the SCS bits and execute SLEEP.
Although the CPU is disabled, the peripherals continue
to be clocked from the primary clock source specified
by the FOSC3:FOSC0 Configuration bits. The OSTS
bit remains set (see Figure 3-7).
When a wake event occurs, the CPU is clocked from the
primary clock source. A delay of interval T
required between the wake event and when code
execution starts. This is required to allow the CPU to
become ready to execute instructions. After the
wake-up, the OSTS bit remains set. The IDLEN and
SCS bits are not affected by the wake-up (see
Figure 3-8).
FIGURE 3-7:
FIGURE 3-8:
DS39625C-page 38
CPU Clock
Peripheral
CPU Clock
Program
Counter
Peripheral
Program
OSC1
Counter
Clock
OSC1
Clock
PRI_IDLE MODE
Q1
Q1
TRANSITION TIMING FOR ENTRY TO IDLE MODE
TRANSITION TIMING FOR WAKE FROM IDLE TO RUN MODE
Wake Event
Q2
PC
Q3
T
CSD
Q4
CSD
Preliminary
is
Q1
PC
executing code being clocked by the Timer1 oscillator.
3.4.2
In SEC_IDLE mode, the CPU is disabled but the
peripherals continue to be clocked from the Timer1
oscillator. This mode is entered from SEC_RUN by set-
ting the IDLEN bit and executing a SLEEP instruction. If
the device is in another Run mode, set the IDLEN bit
first, then set the SCS1:SCS0 bits to ‘01’ and execute
SLEEP. When the clock source is switched to the
Timer1 oscillator, the primary oscillator is shut down,
the OSTS bit is cleared and the T1RUN bit is set.
When a wake event occurs, the peripherals continue to
be clocked from the Timer1 oscillator. After an interval of
T
The IDLEN and SCS bits are not affected by the
wake-up; the Timer1 oscillator continues to run (see
Figure 3-8).
CSD
Note:
following the wake event, the CPU begins
SEC_IDLE MODE
The Timer1 oscillator should already be
running prior to entering SEC_IDLE mode.
If the T1OSCEN bit is not set when the
SLEEP instruction is executed, the SLEEP
instruction will be ignored and entry to
SEC_IDLE mode will not occur. If the
Timer1 oscillator is enabled but not yet run-
ning, peripheral clocks will be delayed until
the oscillator has started. In such situations,
initial oscillator operation is far from stable
and unpredictable operation may result.
PC + 2
Q2
© 2007 Microchip Technology Inc.
Q3
Q4