PIC18F4585-H/ML Microchip Technology, PIC18F4585-H/ML Datasheet - Page 169

• Manufacturer Part Number: PIC18F4585-H/ML
• Description: IC MCU 8BIT 48KB FLASH 44QFN
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F4585-H/ML

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: CAN, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 36
• Program Memory Size: 48KB (24K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 3.25K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 11x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 150°C
• Package / Case: 44-VQFN Exposed Pad
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

15.3
In Compare mode, the 16-bit CCPR1 register value is
constantly compared against either the TMR1 or TMR3
register pair value. When a match occurs, the CCP1
pin can be:
• driven high
• driven low
• toggled (high-to-low or low-to-high)
• remain unchanged (that is, reflects the state of the
The action on the pin is based on the value of the mode
select bits (ECCP1M3:ECCP1M0). At the same time,
the interrupt flag bit ECCP1IF is set.
15.3.1
The user must configure the CCP1 (ECCP1) pin as an
output by clearing the appropriate TRIS bit.
FIGURE 15-2:
© 2007 Microchip Technology Inc.
I/O latch)
Note:
Compare Mode
CCP1 PIN CONFIGURATION
Clearing the CCP1CON register will force
the RC2 compare output latch (depending
on device configuration) to the default low
level. This is not the PORTC I/O data
latch.
0
1
COMPARE MODE OPERATION BLOCK DIAGRAM
ECCPR1H
TMR1H
TMR3H
CCPR1H
T3CCP1
Comparator
Comparator
ECCPR1L
CCPR1L
TMR1L
TMR3L
Compare
Compare
Match
Match
PIC18F2585/2680/4585/4680
1
0
Set CCP1IF
Preliminary
T3ECCP1
Set CCP1IF
(Timer1/Timer3 Reset, A/D Trigger)
15.3.2
Timer1 and/or Timer3 must be running in Timer mode
or Synchronized Counter mode if the CCP1 module is
using the compare feature. In Asynchronous Counter
mode, the compare operation may not work.
15.3.3
When the Generate Software Interrupt mode is chosen
(CCP1M3:CCP1M0 = 1010), the CCP1 pin is not
affected. Only a CCP1 interrupt is generated, if enabled
and the CCP1IE bit is set.
15.3.4
Both CCP1 modules are equipped with a special event
trigger. This is an internal hardware signal generated in
Compare mode to trigger actions by other modules.
The special event trigger is enabled by selecting
the Compare
(CCP1M3:CCP1M0 = 1011).
For either CCP1 module, the special event trigger
resets the timer register pair for whichever timer
resource is currently assigned as the module’s time
base. This allows the CCPR1 (ECCPR1) registers to
serve as a programmable period register for either
timer.
Special Event Trigger
Special Event Trigger
ECCP1CON<3:0>
CCP1CON<3:0>
(Timer1 Reset)
Output
Output
Logic
4
Logic
4
TIMER1/TIMER3 MODE SELECTION
SOFTWARE INTERRUPT MODE
SPECIAL EVENT TRIGGER
Special
S
R
S
R
Q
Q
Output Enable
Output Enable
Event
TRIS
TRIS
DS39625C-page 167
ECCP1 pin
Trigger
CCP1 pin
mode