PIC18F4585-H/ML Microchip Technology, PIC18F4585-H/ML Datasheet - Page 197

• Manufacturer Part Number: PIC18F4585-H/ML
• Description: IC MCU 8BIT 48KB FLASH 44QFN
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F4585-H/ML

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: CAN, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 36
• Program Memory Size: 48KB (24K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 3.25K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 11x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 150°C
• Package / Case: 44-VQFN Exposed Pad
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

17.3.8
In SPI Master mode, module clocks may be operating
at a different speed than when in full power mode; in
the case of the Sleep mode, all clocks are halted.
In most power managed modes, a clock is provided to
the peripherals. That clock should be from the primary
clock source, the secondary clock (Timer1 oscillator at
32.768 kHz) or the INTOSC source. See Section 2.7
“Clock Sources and Oscillator Switching” for
additional information.
In most cases, the speed that the master clocks SPI
data is not important; however, this should be
evaluated for each system.
If MSSP interrupts are enabled, they can wake the
controller from Sleep mode, or one of the Idle modes,
when the master completes sending data. If an exit
from Sleep or Idle mode is not desired, MSSP
interrupts should be disabled.
If the Sleep mode is selected, all module clocks are
halted and the transmission/reception will remain in
that state until the devices wakes. After the device
returns to Run mode, the module will resume
transmitting and receiving data.
In SPI Slave mode, the SPI Transmit/Receive Shift
register operates asynchronously to the device. This
allows the device to be placed in any power managed
mode and data to be shifted into the SPI Transmit/
Receive Shift register. When all 8 bits have been
received, the MSSP interrupt flag bit will be set and if
enabled, will wake the device.
TABLE 17-2:
© 2007 Microchip Technology Inc.
INTCON
PIR1
PIE1
IPR1
TRISA
TRISC
SSPBUF
SSPCON1
SSPSTAT
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the MSSP in SPI mode.
Note 1:
Name
These bits are unimplemented in PIC18F2X8X devices; always maintain these bits clear.
OPERATION IN POWER MANAGED
MODES
PORTA Data Direction Register
PORTC Data Direction Register
Synchronous Serial Port Receive Buffer/Transmit Register
GIE/GIEH PEIE/GIEL TMR0IE
PSPIF
PSPIE
PSPIP
WCOL
Bit 7
SMP
REGISTERS ASSOCIATED WITH SPI OPERATION
(1)
(1)
(1)
SSPOV
ADIE
ADIP
ADIF
Bit 6
CKE
SSPEN
RCIF
RCIE
RCIP
Bit 5
D/A
PIC18F2585/2680/4585/4680
Preliminary
INT0IE
TXIF
TXIE
TXIP
Bit 4
CKP
P
SSPM3
SSPIE
SSPIP
SSPIF
17.3.9
A Reset disables the MSSP module and terminates the
current transfer.
17.3.10
Table 17-1 shows the compatibility between the
standard SPI modes and the states of the CKP and
CKE control bits.
TABLE 17-1:
There is also a SMP bit which controls when the data is
sampled.
RBIE
Bit 3
Standard SPI Mode
S
Terminology
0, 0
0, 1
1, 0
1, 1
TMR0IF
CCP1IF
CCP1IE
CCP1IP
SSPM2
EFFECTS OF A RESET
BUS MODE COMPATIBILITY
Bit 2
R/W
SPI BUS MODES
TMR2IE
TMR2IP
TMR2IF
SSPM1
INT0IF
Bit 1
UA
CKP
Control Bits State
0
0
1
1
TMR1IF
TMR1IE
TMR1IP
SSPM0
RBIF
Bit 0
DS39625C-page 195
BF
CKE
on page
Values
Reset
1
0
1
0
49
52
52
52
52
52
50
50
50