NUC130LE3CN Nuvoton Technology Corporation of America, NUC130LE3CN Datasheet - Page 147

• Manufacturer Part Number: NUC130LE3CN
• Description: IC MCU 32BIT 128KB FLASH 48LQFP
• Manufacturer: Nuvoton Technology Corporation of America
• Series: NuMicro™ NUC100r

Specifications of NUC130LE3CN

• Core Processor: ARM Cortex-M0
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 35
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 8x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-LQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PLL Control Register (PLLCON)
The PLL reference clock input is from the external 4~24 MHz high speed crystal clock input or
from the internal 22.1184 MHz high speed oscillator. These registers are use to control the PLL
output frequency and PLL operating mode
Register
PLLCON
Bits
[31:20]
[19]
[18]
[17]
[16]
[15:14]
[13:9]
[8:0]
31
23
15
7
NuMicro™ NUC130/NUC140 Technical Reference Manual
OUT_DV
Offset
CLK_BA+0x20
Descriptions
Reserved
PLL_SRC
OE
BP
PD
OUT_DV
IN_DV
FB_DV
30
22
14
6
Reserved
R/W
R/W
Reserved
PLL Source Clock Select
1 = PLL source clock from internal 22.1184 MHz high speed oscillator
0 = PLL source clock from external 4~24 MHz high speed crystal
PLL OE (FOUT enable) pin Control
0 = PLL FOUT enable
1 = PLL FOUT is fixed low
PLL Bypass Control
0 = PLL is in normal mode (default)
1 = PLL clock output is same as clock input (XTALin)
Power Down Mode
If set the PWR_DOWN_EN bit to 1 in PWRCON register, the PLL will enter power
down mode too.
0 = PLL is in normal mode
1 = PLL is in power down mode (default)
PLL Output Divider Control Pins
Refer to the formulas below the table.
PLL Input Divider Control Pins
Refer to the formulas below the table.
PLL Feedback Divider Control Pins
29
21
13
5
Description
PLL Control Register
28
20
12
4
- 147 -
Reserved
FB_DV
PLL_SRC
IN_DV
27
19
11
3
Publication Release Date: June 14, 2011
OE
26
18
10
2
BP
25
17
9
1
Revision V2.01
Reset Value
0x0005_C22E
FB_DV
PD
24
16
8
0