NUC130LE3CN Nuvoton Technology Corporation of America, NUC130LE3CN Datasheet - Page 472

• Manufacturer Part Number: NUC130LE3CN
• Description: IC MCU 32BIT 128KB FLASH 48LQFP
• Manufacturer: Nuvoton Technology Corporation of America
• Series: NuMicro™ NUC100r

Specifications of NUC130LE3CN

• Core Processor: ARM Cortex-M0
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 35
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 8x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-LQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

5.16.4.6 External trigger Input Sampling and A/D Conversion Time
5.16.4.7 Conversion Result Monitor by Compare Function
In single-cycle scan mode, A/D conversion can be triggered by external pin request. When the
ADCR.TRGEN is set to high to enable ADC external trigger function, setting the TRGS[1:0] bits to
00b is to select external trigger input from the STADC pin. Software can set TRGCOND[1:0] to
select trigger condition is falling/rising edge or low/high level. If level trigger condition is selected,
the STADC pin must be kept at defined state at least 8 PCLKs. The ADST bit will be set to 1 at
the 9th PCLK and start to conversion. Conversion is continuous if external trigger input is kept at
active state in level trigger mode. It is stopped only when external condition trigger condition
disappears. If edge trigger condition is selected, the high and low state must be kept at least 4
PLCKs. Pulse that is shorter than this specification will be ignored.
ADC controller provide two sets of compare register ADCMPR0 and ADCMPR1, to monitor
maximum two specified channels conversion result from A/D conversion controller, refer to Figure
5-105. Software can select which channel to be monitored by set CMPCH(ADCMPRx[5:0]) and
CMPCOND bit is used to check conversion result is less than specify value or greater than (equal
to) value specified in CMPD[11:0]. When the conversion of the channel specified by CMPCH is
completed, the comparing action will be triggered one time automatically. When the compare
result meets the setting, compare match counter will increase 1, otherwise, the compare match
counter will be clear to 0. When counter value reach the setting of (CMPMATCNT+1) then CMPF
bit will be set to 1, if CMPIE bit is set then an ADC_INT interrupt request is generated. Software
can use it to monitor the external analog input pin voltage transition in scan mode without
imposing a load on software. Detail logics diagram is shown as below:
NuMicro™ NUC130/NUC140 Technical Reference Manual
Figure 5-105 A/D Conversion Result Monitor Logics Diagram
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Publication Release Date: June 14, 2011
Revision V2.01