NUC130LE3CN Nuvoton Technology Corporation of America, NUC130LE3CN Datasheet - Page 297

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NUC130LE3CN

Manufacturer Part Number
NUC130LE3CN
Description
IC MCU 32BIT 128KB FLASH 48LQFP
Manufacturer
Nuvoton Technology Corporation of America
Series
NuMicro™ NUC100r
Datasheets

Specifications of NUC130LE3CN

Core Processor
ARM Cortex-M0
Core Size
32-Bit
Speed
50MHz
Connectivity
CAN, I²C, IrDA, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
Number Of I /o
35
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Eeprom Size
-
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 5.5 V
Data Converters
A/D 8x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
48-LQFP
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
NUC130LE3CN
Manufacturer:
Nuvoton Technology Corporation of America
Quantity:
10 000
Part Number:
NUC130LE3CN
Manufacturer:
NUVOTON
Quantity:
20 000
SPI Divider Register (SPI_DIVIDER)
Register
SPI_DIVIDER SPIx_BA+0x04
Bits
[31:16]
[15:0]
31
23
15
7
NuMicro™ NUC130/NUC140 Technical Reference Manual
Offset
Descriptions
DIVIDER2
DIVIDER
30
22
14
6
R/W
R/W
Clock Divider 2 Register (master only)
The value in this field is the 2
output SPICLK. The desired frequency is obtained according to the following equation:
If VARCLK_EN is cleared to 0, this setting is unmeaning.
Clock Divider Register (master only)
The value in this field is the frequency divider for generating the serial clock on the
output SPICLK. The desired frequency is obtained according to the following equation:
In slave mode, the period of SPI clock driven by a master shall equal or over 5 times
the period of PCLK. In other words, the maximum frequency of SPI clock is the fifth of
the frequency of slave’s PCLK.
f
f
29
21
13
5
sclk
sclk
=
=
Description
Clock Divider Register (Master Only)
(
(
DIVIDER
DIVIDER
28
20
12
f
f
4
DIVIDER2[15:8]
DIVIDER2[7:0]
DIVIDER[15:8]
DIVIDER[7:0]
- 297 -
pclk
pclk
2
+
+
1
1
* )
* )
2
2
nd
frequency divider for generating the serial clock on the
27
19
11
3
Publication Release Date: June 14, 2011
26
18
10
2
25
17
9
1
Revision V2.01
Reset Value
0x0000_0000
24
16
8
0

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