AK4125VFP-E2 AKM Semiconductor Inc, AK4125VFP-E2 Datasheet
AK4125VFP-E2
Specifications of AK4125VFP-E2
Related parts for AK4125VFP-E2
AK4125VFP-E2 Summary of contents
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High Performance Asynchronous SRC The AK4125 is a stereo digital sample rate converter (SRC). The input sample rate ranges from 8kHz to 216kHz. The output sample rate is from 8kHz to 216kHz. The system can take very ...
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Ordering Guide −40 ∼ +85°C AK4125VF AKD4125 Evaluation Board for AK4125 ■ Pin Layout FILT AVSS PDN SMUTE DITHER PLL2 ILRCK IBICK SDTI IDIF0 IDIF1 IDIF2 PLL0 PLL1 UNLOCK MS0379-E-05 30pin VSOP (0.65mm pitch ...
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Compatibility with AK4124 Digital Filter Passband Refer to Table 8 for the detail of filter response. MS0379-E-05 AK4124 0.985 ≤ FSO/FSI ≤ 6.000 0.4583FSI 0.905 ≤ FSO/FSI < 0.985 0.4167FSI 0.714 ≤ FSO/FSI < 0.905 0.3195FSI 0.656 ≤ FSO/FSI ...
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No. Pin Name I/O 1 FILT O 2 AVSS - 3 PDN I 4 SMUTE I 5 DITHER I 6 PLL2 I 7 ILRCK I/O 8 IBICK I/O 9 SDTI I 10 IDIF0 I 11 IDIF1 I 12 IDIF2 I ...
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Handling of Unused pins The unused digital I/O pins should be processed appropriately as below. Classification Pin Name Analog FILT SMUTE, DITHER Digital IMCLK, OMCLK UNLOCK (AVSS=DVSS=0V; Note 1) Parameter Power Supplies: Analog Digital |AVSS − DVSS| Input Current, ...
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AVDD=DVDD=3.3V; AVSS=DVSS=0V; Single Frequency = 1 kHz, data = 24bit; measurement bandwidth = 20Hz ~ FSO/2; unless otherwise specified.) Parameter SRC Characteristics: Resolution Input Sample Rate Output Sample Rate THD+N (Input = 1kHz, 0dBFS, FSO/FSI = 44.1kHz/48kHz FSO/FSI = ...
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AVDD=DVDD=3.0 ∼ 3.6V) Parameter Digital Filter Passband −0.01dB 0.985 ≤ FSO/FSI ≤ 6.000 0.905 ≤ FSO/FSI < 0.985 0.714 ≤ FSO/FSI < 0.905 0.656 ≤ FSO/FSI < 0.714 0.536 ≤ FSO/FSI < 0.656 0.492 ≤ FSO/FSI < 0.536 0.452 ...
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AVDD= DVDD=3.0 ∼ 3.6V) Parameter High-Level Input Voltage Low-Level Input Voltage High-Level Output Voltage Low-Level Output Voltage Input Leakage Current Power Supplies Power Supply Current Normal operation (PDN pin = “H”) FSI=FSO=48kHz at Slave Mode: FSI=FSO=192kHz at Master Mode: ...
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AVDD=DVDD=3.0 ∼ 3.6V; C Parameter Master Clock Timing Frequency Pulse Width Low Pulse Width High LRCK for Input data (ILRCK) Frequency Duty Cycle Slave Mode Master Mode LRCK for Output data (OLRCK) Frequency Duty Cycle Slave Mode Master Mode ...
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Timing Diagram MCLK LRCK BICK LRCK tBLR BICK tLRS SDTO SDTI Note: BICK shows IBICK and OBICK, LRCK shows ILRCK and OLRCK. MS0379-E-05 1/fCLK tCLKH tCLKL 1/fs tBCK tBCKH tBCKL Clock Timing tLRB tBSD tSDS tSDH Audio Interface Timing ...
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LRCK tMBLR BICK SDTO SDTI Note: BICK shows IBICK and OBICK, LRCK shows ILRCK and OLRCK. PDN MS0379-E-05 tBSD tSDS tSDH Audio Interface Timing (Master mode) tPD Power Down & Reset Timing - 11 - [AK4125] 50%DVDD dBCK 50%DVDD 50%DVDD ...
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System Clock & Audio Interface Format for Input PORT The input port works in master mode or slave mode. An internal system clock is created by the internal PLL using ILRCK (Mode 0 ∼ IBICK ...
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ILRCK IBICK(32fs) SDTI( IBICK(64fs) Don't Care SDTI(i) 15:MSB, 0:LSB ILRCK IBICK(64fs) Don't Care SDTI(i) 19:MSB, 0:LSB ILRCK IBICK(64fs) SDTI( 23:MSB, 0:LSB ...
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ILRCK IBICK(64fs) Don't Care SDTI(i) 23:MSB, 0:LSB ■ System Clock & Audio Interface Format for Output PORT The output port works in master mode or slave mode. The MCLK is not needed in slave mode. The CMODE2-0 ...
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OLRCK OBICK(64fs) SDTO(O) 15:MSB, 0:LSB SDTO( 17:MSB, 0:LSB SDTO(O) 19:MSB, 0:LSB SDTO(O) 23:MSB, 0:LSB Lch Data ...
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Soft Mute Operation 1. Manual mode Soft mute operation is performed in the digital domain of the SRC output. Soft mute can be controlled by the SMUTE pin. When the SMUTE pin changes to “H”, the SRC output data ...
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Dither The AK4125 has a dither circuit. The dither circuit adds the dither to the LSB of the output data, which is the value of the OBIT1-0 pins, by DITHER pin = “H” regardless of the SRC mode or ...
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Internal Reset Function for Clock Change The AK4125 is reset automatically when the output clock is stopped. If the output clock is started again, normal data is output within 100ms. ■ Sequence of Changing Clocks The change of the ...
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PLL Loop Filter The C1 and R should be connected in series and attached between FILT pin and AVSS in parallel with C2. Table 6, Table 7) Please be careful the noise onto the FILT pin. When using IBICK, ...
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Figure 15, Figure 16 show the system connection diagram. The evaluation board demonstrates application circuits, the optimum layout, power supply arrangements and measurement results. • Input PORT: Slave Mode, IBICK lock mode (64fsi), 24bit MSB justified • Output PORT: Slave ...
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Input PORT: Slave Mode, IBICK lock mode (64fsi), 24bit MSB justified • Output PORT: Master mode, 24bit MSB justified • Dither = OFF 470 1.0n 0.22μ Reset fsi 64fsi DSP, uP Note: - AVSS and DVSS of the AK4125 ...
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Jitter Tolerance Figure 17 shows the jitter tolerance to ILRCK and IBICK. The jitter quantity is defined by the jitter frequency and the jitter amplitude shown in Figure 17. When the jitter amplitude is 0.01Uipp or less, the AK4125 ...
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Digital Filter Response Example Table 8 shows the examples of digital filter response performed by the AK4125. Ratio FSO/FSI [kHz] 4.000 192/48.0 1.000 48.0/48.0 0.919 44.1/48.0 0.725 32.0/44.1 0.667 32.0/48.0 0.544 48.0/88.2 0.500 48.0/96.0 0.500 44.1/88.2 0.459 44.1/96.0 0.363 ...
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VSOP (Unit: mm) *9.7 ± 0.1 0 0.22 ± 0.1 0.12 M NOTE: Dimension "*" does not include mold flash. ■ Material & Lead finish Package molding compound: Lead frame material: Lead frame surface treatment: MS0379-E-05 PACKAGE ...
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XXXB: Lot number (X: Digit number, B: Alpha character) YYYYC: Assembly date (Y: Digit number, C: Alpha character) Date (YY/MM/DD) Revision 05/01/05 00 05/05/10 01 06/06/20 02 07/02/20 03 07/07/25 04 10/05/17 05 MS0379-E-05 MARKING AKM AK4125VF XXXBYYYYC XXXBYYYYC Date ...
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These products and their specifications are subject to change without notice. When you consider any use or application of these products, please make inquiries the sales office of Asahi Kasei Microdevices Corporation (AKM) or authorized distributors as to current status ...