AK4125VFP-E2 AKM Semiconductor Inc, AK4125VFP-E2 Datasheet - Page 17

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AK4125VFP-E2

Manufacturer Part Number
AK4125VFP-E2
Description
IC SAMPLE RATE CONVERTER 30VSOP
Manufacturer
AKM Semiconductor Inc
Series
-r
Type
Sample Rate Converterr
Datasheet

Specifications of AK4125VFP-E2

Applications
Automotive Systems, Home Theater, TV
Mounting Type
Surface Mount
Package / Case
30-LSSOP (0.220", 5.60mm Width)
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
974-1042-2
The AK4125 has a dither circuit. The dither circuit adds the dither to the LSB of the output data, which is the value of the
OBIT1-0 pins, by DITHER pin = “H” regardless of the SRC mode or the SRC bypass mode.
Bringing the PDN pin = “L” sets the AK4125 power-down mode and initializes the digital filter. The AK4125 should be
reset once by bringing the PDN pin = “L” when power-up. When the PDN pin = “L”, the SDTO output is “L”. The SDTO
valid time is 100ms. Until the output data becomes valid, the SDTO pin outputs “L”.
MS0379-E-05
Dither
System Reset
Case 1
Case 2
External clocks
(Internal state)
External clocks
External clocks
(Internal state)
External clocks
SDTI
SDTO
SDTI
SDTO
UNLOCK
UNLOCK
PDN
PDN
(Input port)
(Input port)
(Output port)
(Output port)
Power-down
Power-down
Don’t care
Don’t care
Don’t care
“0” data
fs detection
PLL lock &
< 100ms
(No Clock)
(Don’t care)
(Don’t care)
Output Clocks 1
Figure 12. System Reset 2
Input Clocks 1
Figure 11. System Reset
Input Data 1
“0” data
PLL Unlock
Normal data
Normal
- 17 -
operation
PD
“0” data
PLL lock &
PLL lock &
fs detection
< 100ms
fs detection
< 100ms
Output Clocks 2
Input Clocks 2
Input Data 2
Output Clocks
Input Clocks
Input Data
Normal data
Normal data
Normal
Normal
operation
operation
Power-down
Don’t care
Don’t care
Don’t care
Power-down
Don’t care
Don’t care
Don’t care
“0” data
“0” data
[AK4125]
2010/05

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