SI3018-F-GSR Silicon Laboratories Inc, SI3018-F-GSR Datasheet - Page 36

• Manufacturer Part Number: SI3018-F-GSR
• Manufacturer: Silicon Laboratories Inc

Specifications of SI3018-F-GSR

• Lead Free Status / Rohs Status: Supplier Unconfirmed

5.28. Transhybrid Balance
The Si3050 contains an on-chip analog hybrid that
performs the 2- to 4-wire conversion and near-end echo
cancellation. This hybrid circuit is adjusted for each ac
termination setting selected to achieve a minimum
transhybrid balance of 20 dB when the line impedance
matches the impedance set by ACIM.
The Si3050 also offers a digital hybrid stage for
additional near-end echo cancellation. For each ac
termination setting, the eight programmable hybrid
registers (Registers 45–52) can be programmed with
coefficients to increase cancellation of real-world line
impedances. This digital filter can produce 10 dB or
greater of near-end echo cancellation in addition to the
trans-hybrid loss from the analog hybrid circuitry.
Coefficients are 2s complement, where unity is
represented as binary 0100 0000b, the maximum value
as binary 0111 1111b, and the minimum value as binary
1000 000b. See AN84 for a more detailed description of
the digital hybrid and how to use it.
Si3050
DTX
DRX
To
Attenuation
Steps
1 dB
RXA2
TXG2
Steps
1 dB
Gain
Link
Digital
Filter
IIRE
TXG3
TXA3
Gain/ATT
0.1 dB
Steps
Figure 25. Si3018/19 Signal Flow Diagram
Gain/ATT
0.1 dB
Steps
Figure 26. Si3050 Signal Flow Diagram
RXG3
RXA3
Digital
Filter
IIRE
Steps
Gain
1 dB
RXG2
DAC
ADC
Rev. 1.31
Selectable
Attenuation
TXA2
200 Hz
Steps
HPF
1 dB
5.29. Filter Selection
The Si3050 supports additional filter selections for the
receive and transmit signals as defined in Tables 10 and
11. The IIRE bit (Register 16, bit 4) selects between the
IIR and FIR filters. The IIR filter provides a shorter, but
non-linear, group delay alternative to the default FIR
filter, and only operates with an 8 kHz sample rate. The
FILT bit (Register 31, bit 1) selects a –3 dB low
frequency pole of 5 Hz when cleared and a –3 dB low
frequency pole of 200 Hz (per EIA/TIA 464) when set.
The FILT bit affects the receive path only.
5.30. Clock Generation
The Si3050 generates the necessary internal clock
frequencies from the PCLK input. PCLK must be
synchronous to the 8 kHz FSYNC clock and run at one
of the following rates: 256 kHz, 512 kHz, 768 kHz,
1.024 MHz,
8.192 MHz. The ratio of the PCLK rate to the FSYNC
rate is determined internally by the DAA and is
transferred into internal registers after a reset. These
internal registers are not accessible through register
reads or writes. Figure 27 shows the operation of the
Si3050 clock circuitry.
Analog
Hybrid
Hybrid
Digital
Si3050 + Si3018/19
1.53 MHz,
ACT
0.6 Hz
HPF
Link
2.048 MHz,
TX
4.09 MHz,
To
Si3018/19
CO
37
or