LS7061 LSI Computer Systems, Inc., LS7061 Datasheet

LS7061

Manufacturer Part Number

LS7061

Description

32bit/dual 16bit binary up counter with byte multiplexed three-state outputs

Manufacturer

LSI Computer Systems, Inc.

Datasheet

1.LS7061.pdf (7 pages)

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7061/63-012703-1

FEATURES:

• DC to 15MHz Count Frequency

• Byte Multiplexer

• DC to 1MHz Scan Frequency

• +4.75V to +5.25V Operation (V

• Latch Provided for External High Speed Counter Byte,

• Three-State Data Outputs, Bus and TTL Compatible

• Inputs TTL and CMOS Compatible

• Unique Cascade Feature Allows Multiplexing of Successive

• LS7061, LS7063 (DIP);

DESCRIPTION:

The LS7061/LS7063 is a MOS, 32 bit/dual 16 bit up counter. The

IC includes 40 latches, multiplexer, eight three-state binary data

output drivers and output cascading logic.

DESCRIPTION OF OPERATION:

32 (16) BIT BINARY UP COUNTER - LS7061 (LS7063)

The 32 (16) bit static ripple through counter increments on the

negative edge of the input count pulse. Maximum ripple time is

4µs (2µs) - transition count of 32 (16) ones to 32 (16) zeros.

Guaranteed count frequency is DC to 15MHz.

See Figure 8A (8B) for Block Diagram.

COUNT - LS7061, COUNT A - LS7063

Input count pulses to the 32 (first 16) bit counter may be applied

through this input. This input is the most significant bit of the ex-

ternal data byte.

COUNT B - LS7063

Count pulses may be applied to the last 16 bits of the binary

counter through this input. The counter advances on the negative

transition of these pulses.

RESET

All 32 counter bits are reset to zero when RESET is brought low

for a minimum of 1µs. RESET must be high for a minimum of

300ns before next valid count can be recorded. COUNT B must

be held low when RESET is brought low to ensure proper reset of

Counter B for LS7063.

TEST COUNT - LS7061

Count pulses may be applied to the last 16 bits of the binary

counter through this input, as long as Bit 16 of the counter is a

low. The counter advances on the negative transition of these

pulses. This input is intended to be used for test purposes.

Effectively Extending Count Frequency to 3.84GHz

Bytes of Data in Sequence in Multiple Counter Systems

LS7061-S, LS7063-S (SOIC) - See Figures 1 & 2

U L

A3800

LSI/CSI

LSI Computer Systems, Inc. 1235 Walt Whitman Road, Melville, NY 11747

WITH BYTE MULTIPLEXED THREE-STATE OUTPUTS

32 BIT/DUAL 16 BIT BINARY UP COUNTER

- V

)

CASCADE ENABLE OUT

LATCHES - LS7061 (LS7063)

40 bits of latch are provided, eight for storage of the contents

of a high speed external prescaling counter and the remaining

32 for the contents of the counter data. All latches are loaded

when the LOAD input is brought low for a minimum of 1µs

and kept low until a minimum of 4µs (2µs) has elapsed from

previous negative edge of count pulse (ripple time). Storage

of valid data occurs when LOAD is brought high for a mini-

mum of 250ns before next negative edge of count pulse or

RESET.

(COUNTA) B7 IN

(COUNT) B7 IN

Vss (-V)

B3 OUT

B2 OUT

B1 OUT

B0 OUT

B3 OUT

B2 OUT

B1 OUT

B0 OUT

R E S E T

B6 IN

B5 IN

B4 IN

B6 IN

B5 IN

B4 IN

(+V)

LS7061/7063

PIN ASSIGNMENT - TOP VIEW

(631) 271-0400 FAX (631) 271-0405

FIGURE 2

FIGURE 1

B4 OUT

B5 OUT

B0 IN

B1 IN

B6 OUT

B2 IN

B7 OUT

B3 IN

TEST COUNT

SCAN RESET/LOAD

ENABLE

SCAN

B4 OUT

B5 OUT

B0 IN

B1 IN

B6 OUT

B2 IN

B7 OUT

B3 IN

COUNT B

SCAN RESET/LOAD

ENABLE

SCAN

January 2003

Related parts for LS7061

LS7061 Summary of contents

Page 1

... Bytes of Data in Sequence in Multiple Counter Systems • LS7061, LS7063 (DIP); LS7061-S, LS7063-S (SOIC) - See Figures 1 & 2 DESCRIPTION: The LS7061/LS7063 is a MOS, 32 bit/dual 16 bit up counter. The IC includes 40 latches, multiplexer, eight three-state binary data output drivers and output cascading logic. DESCRIPTION OF OPERATION: 32 (16) BIT BINARY UP COUNTER - LS7061 (LS7063) The 32 (16) bit static ripple through counter increments on the negative edge of the input count pulse ...

Page 2

SCAN COUNTER AND DECODER The scan counter is reset to the least significant byte position (State 1) when SCAN RESET input is brought low for a mini- mum of 1µs. The scan counter is enabled for counting as long as ...

Page 3

ABSOLUTE MAXIMUM RATINGS: PARAMETER StorageTemperature Operating Temperature Voltage (any pin ELECTRICAL CHARACTERISTICS +5V ± 0˚ 70˚C unless otherwise noted PARAMETER SYMBOL Power ...

Page 4

... Count Pulse Width (All Count Inputs) Count Rise & Fall time (Pins 2, 16) Count Ripple Time (Pin 2 - LS7061) Count Ripple Time (Pin 13 - LS7061) (Pins LS7063) RESET Pulse Width (All Counter Stages Fully Reset) RESET Removal Time (Reset Removed From All Counter Stages) ...

Page 5

RESET COUNT t LOAD RESET SC ENABLE SCAN RESET SCAN 7061/63-012703-5 t RPW CPW RSCR CPW FIGURE 4. COUNTER TIMING DIAGRAM OUTPUT DATA BUS RESET SC FIGURE 5. ...

Page 6

SCAN RESET ENABLE SCAN CASCADE ENABLE A CASCADE ENABLE B CASCADE ENABLE C (END OF SCAN) DATA BYTE ON BUS PACKAGE FIGURE 7. APPLICATION EXAMPLE: HIGH SPEED DIFFERENTIAL ENERGY ANALYZER RADIATION P ...

Page 7

... BIT LATCH (COUNT DATA IN 7061/63-012703-7 FIGURE 8A. LS7061 BLOCK DIAGRAM 6 STATE STATIC SCAN COUNTER AND DECODER C SC (STOPS IN STATE 6 UNTIL SCAN RESET CAUSES RESET TO STATE ONE ST2 ST4 ST5 ST1 ST3 8 BIT MUX BUS MUX MUX G GATE GATE 8 BIT LATCH 8 BIT LATCH ...

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