SAF-C161K-LM Infineon Technologies AG, SAF-C161K-LM Datasheet
SAF-C161K-LM
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SAF-C161K-LM Summary of contents
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... Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies failure of such components can reasonably be expected to cause the failure of that life-support device or system affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body support and/or maintain and sustain and/or protect human life ...
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C161K/O Revision History: Previous Version: Page Subjects (major changes since last revision) All Converted to Infineon layout All C161V removed 2 Ordering Codes and Cross-Reference replaced with Derivative Synopsis Open drain functionality described for P2, P3, P6 ...
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Single-Chip Microcontroller C166 Family C161K/O • High Performance 16-bit CPU with 4-Stage Pipeline – Instruction Cycle Time at 25 MHz CPU Clock – 400 ns Multiplication (16 – Enhanced Boolean Bit Manipulation Facilities – Additional Instructions to ...
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... As this document refers to all of these derivatives, some descriptions may not apply to a specific product. Table 1 C161K/O Derivative Synopsis 1) Derivative SAF-C161K-LM SAB-C161K-LM SAF-C161K-L25M SAB-C161K-L25M SAF-C161K-LM3V SAB-C161K-LM3V SAF-C161O-LM SAB-C161O-LM SAF-C161O-L25M SAB-C161O-L25M SAF-C161O-LM3V SAB-C161O-LM3V 1) This Data Sheet is valid for devices starting with and including design step HA. ...
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Introduction The C161K derivative of the Infineon C166 Family of full featured single-chip CMOS microcontrollers. It combines high CPU performance (up to 12.5 million instructions per second) with peripheral functionality and enhanced IO-capabilities. The C161K/O is especially suited ...
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Pin Configuration MQFP Package (top view XTAL1 2 XTAL2 P3.2/CAPIN 5 P3.3/T3OUT 6 P3.4/T3EUD 7 P3.5/T4IN 8 P3.6/T3IN 9 P3.7/T2IN 10 P3.8/MRST 11 P3.9/MTSR 12 P3.10/TxD0 13 P3.11/RxD0 14 P3.12/BHE/WRH 15 P3.13/SCLK 16 ...
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Table 2 Pin Definitions and Functions Symbol Pin Input Num Outp. XTAL1 2 I XTAL2 P3.8 11 I/O ...
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Table 2 Pin Definitions and Functions (cont’d) Symbol Pin Input Num Outp WR WRL ALE PORT0 IO P0L.0-7 29-36 P0H.0-7 39-46 PORT1 IO P1L.0-7 47-54 P1H.0-7 55-62 Data Sheet Function ...
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... C161K/O. An internal pullup resistor permits power-on reset using only V a capacitor connected to pulses < 10 ns. Input pulses >100 ns safely pass the filter. The minimum duration for a safe recognition should be 100 CPU clock cycles. In bidirectional reset mode (enabled by setting bit BDRSTEN ...
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Table 2 Pin Definitions and Functions (cont’d) Symbol Pin Input Num Outp P2 P2. P2. P2. P5. P5. ...
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Functional Description The architecture of the C161K/O combines advantages of both RISC and CISC processors and of advanced peripheral subsystems in a very well-balanced way. In addition the on-chip memory blocks allow the design of compact systems with maximum performance. ...
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Memory Organization The memory space of the C161K/O is configured in a Von Neumann architecture which means that code memory, data memory, registers and I/O ports are organized within the same linear address space which includes 16 MBytes. The entire ...
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External Bus Controller All of the external memory accesses are performed by a particular on-chip External Bus Controller (EBC). It can be programmed either to Single Chip Mode when no external memory is required one of four different ...
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Central Processing Unit (CPU) The main core of the CPU consists of a 4-stage instruction pipeline, a 16-bit arithmetic and logic unit (ALU) and dedicated SFRs. Additional hardware has been spent for a separate multiply and divide unit, a bit-mask ...
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The CPU has a register context consisting wordwide GPRs at its disposal. These 16 GPRs are physically allocated within the on-chip RAM area. A Context Pointer (CP) register determines the base address of the active register ...
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Interrupt System With an interrupt response time within a range from just CPU clocks (in case of internal program execution), the C161K/O is capable of reacting very fast to the occurrence of non-deterministic events. The architecture of ...
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Table 3 C161K/O Interrupt Nodes Source of Interrupt or PEC Service Request External Interrupt 1 External Interrupt 2 External Interrupt 3 External Interrupt 4 External Interrupt 5 External Interrupt 6 External Interrupt 7 GPT1 Timer 2 GPT1 Timer 3 GPT1 ...
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The C161K/O also provides an excellent mechanism to identify and to process exceptions or error conditions that arise during run-time, so-called ‘Hardware Traps’. Hardware traps cause immediate non-maskable system reaction which is similar to a standard interrupt service (branching to ...
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General Purpose Timer (GPT) Unit The GPT unit represents a very flexible multifunctional timer/counter structure which may be used for many different time related tasks such as event timing and counting, pulse width and duty cycle measurements, pulse generation, or ...
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T2EUD CPU T2IN CPU T3IN T3EUD T4IN CPU T4EUD … 10 Figure 5 Block Diagram of GPT1 With its maximum resolution of ...
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The capture trigger (timer T5 to CAPREL) may also be generated upon transitions of GPT1 timer T3’s inputs T3IN and/or T3EUD. This is especially advantageous when T3 operates in Incremental Interface Mode. Note: Block GPT2 is only available in the ...
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Serial Channels Serial communication with other microcontrollers, processors, terminals or external peripheral components is provided by two serial interfaces with different functionality, an Asynchronous/Synchronous Serial Channel (ASC0) and a High-Speed Synchronous Serial Channel (SSC). The ASC0 is upward compatible with ...
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... Watchdog Timer The Watchdog Timer represents one of the fail-safe mechanisms which have been implemented to prevent the controller from malfunctioning for longer periods of time. The Watchdog Timer is always enabled after a reset of the chip, and can only be disabled in the time interval until the EINIT (end of initialization) instruction has been executed. Thus, the chip’ ...
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Instruction Set Summary Table 5 lists the instructions of the C161K condensed way. The various addressing modes that can be used with a specific instruction, the operation of the instructions, parameters for conditional execution of instructions, and the ...
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Table 5 Instruction Set Summary (cont’d) Mnemonic Description MOV(B) Move word (byte) data MOVBS Move byte operand to word operand with sign extension MOVBZ Move byte operand to word operand. with zero extension JMPA, JMPI, Jump absolute/indirect/relative ...
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Special Function Registers Overview The following table lists all SFRs which are implemented in the C161K/O in alphabetical order. Bit-addressable SFRs are marked with the letter “b” in column “Name”. SFRs within the Extended SFR-Space (ESFRs) are marked with the ...
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Table 6 C161K/O Registers, Ordered by Name (cont’d) Name Physical Address DP0H b F102 H DP0L b F100 H DP1H b F106 H DP1L b F104 H DP2 b FFC2 H DP3 b FFC6 H DP4 b FFCA H DP6 ...
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Table 6 C161K/O Registers, Ordered by Name (cont’d) Name Physical Address P3 b FFC4 FFC8 FFA2 FFCC H PECC0 FEC0 H PECC1 FEC2 H PECC2 FEC4 H PECC3 FEC6 H PECC4 ...
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Table 6 C161K/O Registers, Ordered by Name (cont’d) Name Physical Address SSCEIC b FF76 H SSCRB F0B2 H SSCRIC b FF74 H SSCTB F0B0 H SSCTIC b FF72 H STKOV FE14 H STKUN FE16 H SYSCON b FF12 H T2 ...
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Absolute Maximum Ratings Table 7 Absolute Maximum Rating Parameters Parameter Storage temperature Junction temperature V Voltage on pins with DD V respect to ground ( ) SS Voltage on any pin with V respect to ground ( ) SS Input ...
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... > < Unit Notes V Active mode MHz CPUmax V Power Down mode V Active mode MHz CPUmax V Power Down mode V Reference voltage 2)3) mA Per pin – C SAB-C161K/O … C SAF-C161K/O … C SAK-C161K/O … - 0.5 V). The absolute sum of input overload V2.0, 2001-01 C161K C161O ...
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Parameter Interpretation The parameters listed in the following partly represent the characteristics of the C161K/ O and partly its demands on the system. To aid in interpreting the parameters right, when evaluating them for a design, they are marked in ...
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DC Characteristics (Standard Supply Voltage Range) (cont’d) (Operating Conditions apply) Parameter 4) RSTIN active current 7) RD/WR inact. current 7) RD/WR active current 7) ALE inactive current 7) ALE active current 7) Port 6 inactive current 7) Port 6 active ...
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DC Characteristics (Reduced Supply Voltage Range) (Operating Conditions apply) Parameter Input low voltage (TTL, all except XTAL1) Input low voltage XTAL1 Input high voltage (TTL, all except RSTIN and XTAL1) Input high voltage RSTIN (when operated as input) Input high ...
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DC Characteristics (Reduced Supply Voltage Range) (cont’d) (Operating Conditions apply) Parameter PORT0 configuration current XTAL1 input current 8) Pin capacitance (digital inputs/outputs) 1) Keeping signal levels within the levels specified in this table, ensures operation without overload conditions. For signal ...
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Power Consumption C161K/O (Standard Supply Voltage Range) (Operating Conditions apply) Parameter Power supply current (active) with all peripherals active Idle mode supply current with all peripherals active Power-down mode supply current 1) The supply current is a function of the ...
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I mA 100 Figure 7 Supply/Idle Current as a Function of Operating Frequency Data Sheet C161K C161O I DD5max I DD5typ I DD3max I DD3typ I IDX5max I IDX3max I ...
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AC Characteristics Definition of Internal Timing The internal operation of the C161K/O is controlled by the internal CPU clock edges of the CPU clock can trigger internal (e.g. pipeline) or external (e.g. bus cycles) operations. The specification of the external ...
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Table 9 C161K/O Clock Generation Modes CLKCFG CPU Frequency f f (P0H.7-5) = CPU OSC OSC OSC 1) The maximum frequency depends on the duty cycle of the external ...
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AC Characteristics Table 10 External Clock Drive XTAL1 (Standard Supply Voltage Range) (Operating Conditions apply) Parameter Symbol t Oscillator period SR 40 OSC 1) t High time Low time Rise ...
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V DD Figure 9 External Clock Drive XTAL1 Note: If the on-chip oscillator is used together with a crystal, the oscillator frequency is limited to a range of 4 MHz to 40 MHz strongly recommended to measure ...
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Testing Waveforms 2 inputs during testing are driven at 2.4 V for a logic 1’ and 0.45 V for a logic 0’. Timing measurements are made at Figure 10 Input Output Waveforms V + 0.1 V ...
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Memory Cycle Variables The timing tables below use three variables which are derived from the BUSCONx registers and represent the special characteristics of the programmed memory cycle. The following table describes, how these variables are to be computed. Table 12 ...
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Multiplexed Bus (Standard Supply Voltage Range) (cont’d) (Operating Conditions apply) ALE cycle time = 6 TCL + 2 Parameter RD, WR low time (no RW-delay valid data in (with RW-delay valid data in (no RW-delay) ALE ...
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Multiplexed Bus (Standard Supply Voltage Range) (cont’d) (Operating Conditions apply) ALE cycle time = 6 TCL + 2 Parameter Address float after RdCS, WrCS (with RW delay) Address float after RdCS, WrCS (no RW delay) RdCS to Valid Data In ...
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AC Characteristics Multiplexed Bus (Reduced Supply Voltage Range) (Operating Conditions apply) ALE cycle time = 6 TCL + 2 Parameter ALE high time Address setup to ALE Address hold after ALE ALE falling edge to RD, WR (with RW-delay) ALE ...
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Multiplexed Bus (Reduced Supply Voltage Range) (cont’d) (Operating Conditions apply) ALE cycle time = 6 TCL + 2 Parameter Data float after RD Data valid to WR Data hold after WR ALE rising edge after RD, WR Address hold after ...
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Multiplexed Bus (Reduced Supply Voltage Range) (cont’d) (Operating Conditions apply) ALE cycle time = 6 TCL + 2 Parameter Data valid to WrCS Data hold after RdCS Data float after RdCS Address hold after RdCS, WrCS Data hold after WrCS ...
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ALE CSxL A21-A16 (A15-A8) BHE, CSxE Read Cycle BUS RD RdCSx Write Cycle BUS WR, WRL, WRH WrCSx Figure 12 External Memory Cycle: Multiplexed Bus, With Read/Write Delay, Normal ALE Data Sheet ...
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ALE CSxL A21-A16 (A15-A8) BHE, CSxE t 6 Read Cycle BUS RD RdCSx Write Cycle BUS WR, WRL, WRH WrCSx Figure 13 External Memory Cycle: Multiplexed Bus, With Read/Write Delay, Extended ALE Data Sheet ...
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ALE CSxL A21-A16 (A15-A8) BHE, CSxE Read Cycle BUS RD RdCSx Write Cycle BUS WR, WRL, WRH WrCSx Figure 14 External Memory Cycle: Multiplexed Bus, No Read/Write Delay, Normal ALE Data Sheet ...
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ALE CSxL A21-A16 (A15-A8) BHE, CSxE t 6 Read Cycle BUS RD RdCSx Write Cycle BUS WR, WRL, WRH WrCSx Figure 15 External Memory Cycle: Multiplexed Bus, No Read/Write Delay, Extended ALE Data Sheet ...
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AC Characteristics Demultiplexed Bus (Standard Supply Voltage Range) (Operating Conditions apply) ALE cycle time = 4 TCL + 2 Parameter ALE high time Address setup to ALE ALE falling edge to RD, WR (with RW-delay) ALE falling edge to RD, ...
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Demultiplexed Bus (Standard Supply Voltage Range) (cont’d) (Operating Conditions apply) ALE cycle time = 4 TCL + 2 Parameter Data valid to WR Data hold after WR ALE rising edge after RD Address hold after WR 3) ALE ...
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Demultiplexed Bus (Standard Supply Voltage Range) (cont’d) (Operating Conditions apply) ALE cycle time = 4 TCL + 2 Parameter Data float after RdCS 1) (with RW-delay) Data float after RdCS 1) (no RW-delay) Address hold after RdCS, WrCS Data hold ...
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AC Characteristics Demultiplexed Bus (Reduced Supply Voltage Range) (Operating Conditions apply) ALE cycle time = 4 TCL + 2 Parameter ALE high time Address setup to ALE ALE falling edge to RD, WR (with RW-delay) ALE falling edge to RD, ...
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Demultiplexed Bus (Reduced Supply Voltage Range) (cont’d) (Operating Conditions apply) ALE cycle time = 4 TCL + 2 Parameter Data valid to WR Data hold after WR ALE rising edge after RD Address hold after WR 3) ALE ...
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Demultiplexed Bus (Reduced Supply Voltage Range) (cont’d) (Operating Conditions apply) ALE cycle time = 4 TCL + 2 Parameter Data float after RdCS 1) (with RW-delay) Data float after RdCS 1) (no RW-delay) Address hold after RdCS, WrCS Data hold ...
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ALE CSxL A21-A16 A15-A0 BHE, CSxE Read Cycle BUS (D15-D8) D7-D0 RD RdCSx Write Cycle BUS (D15-D8) D7-D0 WR, WRL, WRH WrCSx Figure 16 External Memory Cycle: Demultiplexed Bus, With Read/Write Delay, Normal ALE Data Sheet ...
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ALE CSxL A21-A16 A15-A0 BHE, CSxE t 6 Read Cycle BUS (D15-D8) D7-D0 RD RdCSx Write Cycle BUS (D15-D8) D7-D0 WR, WRL, WRH WrCSx Figure 17 External Memory Cycle: Demultiplexed Bus, With Read/Write Delay, Extended ALE Data Sheet ...
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ALE CSxL A21-A16 A15-A0 BHE, CSxE Read Cycle BUS (D15-D8) D7-D0 RD RdCSx Write Cycle BUS (D15-D8) D7-D0 WR, WRL, WRH WrCSx Figure 18 External Memory Cycle: Demultiplexed Bus, No Read/Write Delay, Normal ALE Data Sheet ...
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ALE CSxL A21-A16 A15-A0 BHE, CSxE t 6 Read Cycle BUS (D15-D8) D7-D0 RD RdCSx Write Cycle BUS (D15-D8) D7-D0 WR, WRL, WRH WrCSx Figure 19 External Memory Cycle: Demultiplexed Bus, No Read/Write Delay, Extended ALE Data Sheet ...
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Package Outlines P-MQFP-80-1 (SMD) (Plastic Metric Quad Flat Package) 0.65 0.3 ±0. Index Marking 1) Does not include plastic or metal protrusions of 0.25 max per side Sorts of Packing Package outlines for tubes, trays etc. are ...
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