SAF-C161S-LM 3V AA Infineon Technologies, SAF-C161S-LM 3V AA Datasheet
SAF-C161S-LM 3V AA
Specifications of SAF-C161S-LM 3V AA
SAF-C161S-LM3VAA
SAF-C161S-LM3VAAINTR
SAF-C161S-LM3VAATR
SAF-C161S-LM3VAATR
SAFC161SLM3VAAXT
SP000014948
Related parts for SAF-C161S-LM 3V AA
SAF-C161S-LM 3V AA Summary of contents
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C161S ...
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... Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies failure of such components can reasonably be expected to cause the failure of that life-support device or system affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body support and/or maintain and sustain and/or protect human life ...
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C161S ...
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C161S Revision History: Previous Version: Page Subjects (major changes since last revision) We Listen to Your Comments Any information within this document that you feel is wrong, unclear or missing at all? Your feedback will help us to continuously improve ...
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Single-Chip Microcontroller C166 Family C161S 1 Summary of Features • High Performance 16-bit CPU with 4-Stage Pipeline – Instruction Cycle Time at 25 MHz CPU Clock – 400 ns Multiplication (16 – Enhanced Boolean Bit Manipulation Facilities ...
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... Table 1 C161S Derivative Synopsis Derivative SAB-C161S-L25M SAF-C161S-L25M SAB-C161S-LM3V SAF-C161S-LM3V For simplicity all versions are referred to by the term C161S throughout this document. Ordering Information The ordering code for Infineon microcontrollers provides an exact reference to the required product. This ordering code identifies: • ...
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General Device Information 2.1 Introduction The C161S is a derivative of the Infineon C166 Family of full featured single-chip CMOS microcontrollers. It combines high CPU performance (up to 12.5 million instructions per second) with high peripheral functionality and enhanced ...
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Pin Configuration and Definition XTAL1 2 XTAL2 P3.2/CAPIN 5 P3.3/T3OUT 6 P3.4/T3EUD 7 P3.5/T4IN 8 P3.6/T3IN 9 P3.7/T2IN 10 P3.8/MRST 11 P3.9/MTSR 12 P3.10/TxD0 13 P3.11/RxD0 14 P3.12/BHE/WRH 15 P3.13/SCLK 16 P4.0/A16 ...
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Table 2 Pin Definitions and Functions Symbol Pin Input No. Outp. XTAL1 2 I XTAL2 P3.8 11 I/O ...
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Table 2 Pin Definitions and Functions (cont’d) Symbol Pin Input No. Outp WR WRL ALE PORT0 IO P0L.0-7 29-36 P0H.0-7 39-46 Data Sheet Function External Memory Read Strobe ...
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... SS A spike filter suppresses input pulses < 10 ns. Input pulses > 100 ns safely pass the filter. The minimum duration for a safe recognition should be 100 CPU clock cycles. In bidirectional reset mode (enabled by setting bit BDRSTEN in register SYSCON) the RSTIN line is internally pulled low for the duration of the internal reset sequence upon any reset (HW, SW, WDT) ...
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Table 2 Pin Definitions and Functions (cont’d) Symbol Pin Input No. Outp P2. P2. P2. ...
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Note: The following behavioural differences must be observed when the bidirectional reset is active: • Bit BDRSTEN in register SYSCON cannot be changed after EINIT and is cleared automatically after a reset. • The reset indication flags always indicate a ...
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Functional Description The architecture of the C161S combines advantages of both RISC and CISC processors and of advanced peripheral subsystems in a very well-balanced way. In addition the on- chip memory blocks allow the design of compact systems with ...
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Memory Organization The memory space of the C161S is configured in a von Neumann architecture which means that code memory, data memory, registers and I/O ports are organized within the same linear address space which includes 16 Mbytes. The ...
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External Bus Controller All of the external memory accesses are performed by a particular on-chip External Bus Controller (EBC). It can be programmed either to Single Chip Mode when no external memory is required one of four ...
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Central Processing Unit (CPU) The main core of the CPU consists of a 4-stage instruction pipeline, a 16-bit arithmetic and logic unit (ALU) and dedicated SFRs. Additional hardware has been spent for a separate multiply and divide unit, a ...
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A system stack 1024 words is provided as a storage for temporary data. The system stack is allocated in the on-chip RAM area, and it is accessed by the CPU via the stack pointer (SP) register. Two ...
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Interrupt System With an interrupt response time within a range from just CPU clocks (in case of internal program execution), the C161S is capable of reacting very fast to the occurrence of non-deterministic events. The architecture ...
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Table 3 C161S Interrupt Nodes Source of Interrupt or PEC Service Request Unassigned node External Interrupt 1 External Interrupt 2 External Interrupt 3 External Interrupt 4 External Interrupt 5 External Interrupt 6 External Interrupt 7 GPT1 Timer 2 GPT1 Timer ...
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The C161S also provides an excellent mechanism to identify and to process exceptions or error conditions that arise during run-time, so-called ‘Hardware Traps’. Hardware traps cause immediate non-maskable system reaction which is similar to a standard interrupt service (branching to ...
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General Purpose Timer (GPT) Unit The GPT unit represents a very flexible multifunctional timer/counter structure which may be used for many different time related tasks such as event timing and counting, pulse width and duty cycle measurements, pulse generation, ...
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T2EUD CPU T2IN CPU T3IN T3EUD T4IN CPU T4EUD … 10 Figure 5 Block Diagram of GPT1 With its maximum resolution of ...
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The capture trigger (timer T5 to CAPREL) may also be generated upon transitions of GPT1 timer T3’s inputs T3IN and/or T3EUD. This is especially advantageous when T3 operates in Incremental Interface Mode SYS Control T3IN/ ...
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Real Time Clock The Real Time Clock (RTC) module of the C161S consists of a chain of 3 divider blocks, a fixed 8:1 divider, the reloadable 16-bit timer T14, and the 32-bit RTC timer (accessible via registers RTCH and ...
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Serial Channels Serial communication with other microcontrollers, processors, terminals or external peripheral components is provided by two serial interfaces with different functionality, an Asynchronous/Synchronous Serial Channel (ASC0) and a High-Speed Synchronous Serial Channel (SSC). The ASC0 is upward compatible ...
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... Watchdog Timer The Watchdog Timer represents one of the fail-safe mechanisms which have been implemented to prevent the controller from malfunctioning for longer periods of time. The Watchdog Timer is always enabled after a reset of the chip, and can only be disabled in the time interval until the EINIT (end of initialization) instruction has been executed. Thus, the chip’ ...
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Oscillator Watchdog The Oscillator Watchdog (OWD) monitors the clock signal generated by the on-chip oscillator (either with a crystal or via external clock drive). For this operation the PLL provides a clock signal which is used to supervise transitions ...
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Power Management The C161S provides several means to control the power it consumes either at a given time or averaged over a certain timespan. Three mechanisms can be used (partly in parallel): • Power Saving Modes switch the C161S ...
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Instruction Set Summary Table 5 lists the instructions of the C161S in a condensed way. The various addressing modes that can be used with a specific instruction, the operation of the instructions, parameters for conditional execution of instructions, and ...
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Table 5 Instruction Set Summary (cont’d) Mnemonic Description MOV(B) Move word (byte) data MOVBS Move byte operand to word operand with sign extension MOVBZ Move byte operand to word operand with zero extension JMPA, JMPI, Jump absolute/indirect/relative if condition is ...
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Special Function Registers Overview Table 6 lists all SFRs which are implemented in the C161S in alphabetical order. The following markings assist in classifying the listed registers: “b” in the “Name” column marks Bit-addressable SFRs. “E” in the “Physical ...
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Table 6 C161S Registers, Ordered by Name (cont’d) Name Physical Address CP FE10 H CRIC b FF6A H CSP FE08 H DP0H b F102 H DP0L b F100 H DP1H b F106 H DP1L b F104 H DP2 b FFC2 ...
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Table 6 C161S Registers, Ordered by Name (cont’d) Name Physical Address P0L b FF00 H P1H b FF06 H P1L b FF04 FFC0 FFC4 FFC8 FFA2 H P6 ...
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Table 6 C161S Registers, Ordered by Name (cont’d) Name Physical Address S0TBUF FEB0 H S0TIC b FF6C H SP FE12 H SSCBR F0B4 H SSCCON b FFB2 H SSCEIC b FF76 H SSCRB F0B2 H SSCRIC b FF74 H SSCTB ...
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Table 6 C161S Registers, Ordered by Name (cont’d) Name Physical Address T5IC b FF66 H T6 FE48 H T6CON b FF48 H T6IC b FF68 H TFR b FFAC H WDT FEAE H WDTCON b FFAE H XP0IC b F186 ...
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Electrical Parameters 4.1 Absolute Maximum Ratings Table 7 Absolute Maximum Rating Parameters Parameter Storage temperature Junction temperature V Voltage on pins with DD V respect to ground ( ) SS Voltage on any pin with V respect to ground ...
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... < Electrical Parameters Unit Notes V Active mode MHz CPUmax V Power down mode V Active mode MHz CPUmax V Power down mode V Reference voltage 2)3) mA Per pin – C SAB-C161S … C SAF-C161S … C SAK-C161S … - 0.5 V). The absolute sum of input overload V1.0, 2003-11 C161S ...
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Parameter Interpretation The parameters listed in the following partly represent the characteristics of the C161S and partly its demands on the system. To aid in interpreting the parameters right, when evaluating them for a design, they are marked in ...
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DC Parameters Table 9 DC Characteristics (Standard Supply Voltage Range) (Operating Conditions apply) Parameter Input low voltage (TTL, all except XTAL1) Input low voltage XTAL1 Input high voltage (TTL, all except RSTIN and XTAL1) Input high voltage RSTIN (when ...
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Table 9 DC Characteristics (Standard Supply Voltage Range) (cont’d) (Operating Conditions apply) Parameter 7) Port 6 active current PORT0 configuration current XTAL1 input current 8) Pin capacitance (digital inputs/outputs) 1) Keeping signal levels within the levels specified in this table, ...
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Table 10 DC Characteristics (Reduced Supply Voltage Range) (Operating Conditions apply) Parameter Input low voltage (TTL, all except XTAL1) Input low voltage XTAL1 Input high voltage (TTL, all except RSTIN and XTAL1) Input high voltage RSTIN (when operated as input) ...
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Table 10 DC Characteristics (Reduced Supply Voltage Range) (cont’d) (Operating Conditions apply) Parameter PORT0 configuration current XTAL1 input current 8) Pin capacitance (digital inputs/outputs) 1) Keeping signal levels within the levels specified in this table, ensures operation without overload conditions. ...
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Table 11 Power Consumption C161S (Standard Supply Voltage Range) (Operating Conditions apply) Parameter Power supply current (active) with all peripherals active Idle mode supply current with all peripherals active Idle mode supply current with all peripherals deactivated, PLL off, SDD ...
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Table 12 Power Consumption C161S (Reduced Supply Voltage Range) (Operating Conditions apply) Parameter Power supply current (active) with all peripherals active Idle mode supply current with all peripherals active Idle mode supply current with all peripherals deactivated, PLL off, SDD ...
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I [mA] 100 Figure 8 Supply and Idle Current as a Function of Operating Frequency Data Sheet C161S Electrical Parameters I DD5max I DD5typ I DD3max I DD3typ I IDX5max I IDX5typ ...
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3000 2500 1500 1000 500 10 Figure 9 Sleep and Power Down Supply Current as a Function of Oscillator Frequency Data Sheet C161S Electrical Parameters I IDO5max I IDO5typ I IDO3max I IDO3typ I ...
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Timing Characteristics 5.1 Definition of Internal Timing The internal operation of the C161S is controlled by the internal CPU clock edges of the CPU clock can trigger internal (e.g. pipeline) or external (e.g. bus cycles) operations. The specification of ...
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PORT0 (P0H), i.e. bitfield CLKCFG represents the logic levels on pins P0.15-13 (P0H.7-5). Table 13 associates the combinations of these three bits with the respective clock generation mode. Table 13 C161S Clock Generation ...
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The timings listed in the AC Characteristics that refer to TCLs therefore must be calculated using the minimum TCL that is possible under the respective circumstances. The actual minimum value for TCL depends on the jitter of the PLL. As ...
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Direct Drive When direct drive is configured (CLKCFG = 011 disabled and the CPU clock is directly driven from the internal oscillator with the input clock signal. f The frequency of directly follows the frequency of CPU f (i.e. the ...
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External Clock Drive XTAL1 Table 14 External Clock Drive XTAL1 (Operating Conditions apply) Parameter Symbol t Oscillator SR 40 OSC period 2) t High time Low time Rise time ...
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Testing Waveforms 2 inputs during testing are driven at 2.4 V for a logic 1’ and 0.45 V for a logic 0’. Timing measurements are made at Figure 13 Input Output Waveforms V + 0.1 ...
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Memory Cycle Variables The timing tables below use three variables which are derived from the BUSCONx registers and represent the special characteristics of the programmed memory cycle. Table 15 describes, how these variables are to be computed. Table 15 Memory ...
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Table 16 Multiplexed Bus (Standard Supply Voltage Range) (cont’d) (Operating Conditions apply) ALE cycle time = 6 TCL + 2 Parameter RD, WR low time (with RW-delay) RD, WR low time (no RW-delay valid data in (with RW-delay) ...
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Table 16 Multiplexed Bus (Standard Supply Voltage Range) (cont’d) (Operating Conditions apply) ALE cycle time = 6 TCL + 2 Parameter ALE fall. edge to RdCS, WrCS (with RW delay) ALE fall. edge to RdCS, WrCS (no RW delay) Address ...
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Table 17 Multiplexed Bus (Reduced Supply Voltage Range) (Operating Conditions apply) ALE cycle time = 6 TCL + 2 Parameter ALE high time Address setup to ALE Address hold after ALE ALE falling edge to RD, WR (with RW-delay) ALE ...
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Table 17 Multiplexed Bus (Reduced Supply Voltage Range) (cont’d) (Operating Conditions apply) ALE cycle time = 6 TCL + 2 Parameter Data valid to WR Data hold after WR ALE rising edge after RD, WR Address hold after RD, WR ...
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Table 17 Multiplexed Bus (Reduced Supply Voltage Range) (cont’d) (Operating Conditions apply) ALE cycle time = 6 TCL + 2 Parameter Data valid to WrCS Data hold after RdCS Data float after RdCS Address hold after RdCS, WrCS Data hold ...
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ALE CSxL A23-A16 (A15-A8) BHE, CSxE t Read Cycle BUS RD RdCSx Write Cycle BUS WR, WRL, WRH WrCSx Figure 15 External Memory Cycle: Multiplexed Bus, With Read/Write Delay, Normal ALE Data Sheet ...
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ALE t 38 CSxL A23-A16 (A15-A8) BHE, CSxE t 6 Read Cycle BUS RD RdCSx Write Cycle BUS WR, WRL, WRH WrCSx Figure 16 External Memory Cycle: Multiplexed Bus, With Read/Write Delay, Extended ALE Data Sheet t 16 ...
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ALE CSxL A23-A16 (A15-A8) BHE, CSxE Read Cycle BUS RD RdCSx Write Cycle BUS WR, WRL, WRH WrCSx Figure 17 External Memory Cycle: Multiplexed Bus, No Read/Write Delay, Normal ALE Data Sheet ...
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ALE t 38 CSxL A23-A16 (A15-A8) BHE, CSxE t 6 Read Cycle BUS RD RdCSx Write Cycle BUS WR, WRL, WRH WrCSx Figure 18 External Memory Cycle: Multiplexed Bus, No Read/Write Delay, Extended ALE Data Sheet t 16 ...
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Table 18 Demultiplexed Bus (Standard Supply Voltage Range) (Operating Conditions apply) ALE cycle time = 4 TCL + 2 Parameter ALE high time Address setup to ALE ALE falling edge to RD, WR (with RW-delay) ALE falling edge to RD, ...
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Table 18 Demultiplexed Bus (Standard Supply Voltage Range) (cont’d) (Operating Conditions apply) ALE cycle time = 4 TCL + 2 Parameter Data hold after WR ALE rising edge after RD Address hold after WR 3) ALE falling edge ...
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Table 18 Demultiplexed Bus (Standard Supply Voltage Range) (cont’d) (Operating Conditions apply) ALE cycle time = 4 TCL + 2 Parameter Data float after RdCS 1) (no RW-delay) Address hold after RdCS, WrCS Data hold after WrCS t 1) RW-delay ...
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Table 19 Demultiplexed Bus (Reduced Supply Voltage Range) (Operating Conditions apply) ALE cycle time = 4 TCL + 2 Parameter ALE high time Address setup to ALE ALE falling edge to RD, WR (with RW-delay) ALE falling edge to RD, ...
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Table 19 Demultiplexed Bus (Reduced Supply Voltage Range) (cont’d) (Operating Conditions apply) ALE cycle time = 4 TCL + 2 Parameter Data hold after WR ALE rising edge after RD Address hold after WR 3) ALE falling edge ...
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Table 19 Demultiplexed Bus (Reduced Supply Voltage Range) (cont’d) (Operating Conditions apply) ALE cycle time = 4 TCL + 2 Parameter Data float after RdCS 1) (no RW-delay) Address hold after RdCS, WrCS Data hold after WrCS t 1) RW-delay ...
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ALE CSxL A23-A16 A15-A0 BHE, CSxE t Read Cycle BUS (D15-D8) D7-D0 RD RdCSx Write Cycle BUS (D15-D8) D7-D0 WR, WRL, WRH WrCSx Figure 19 External Memory Cycle: Demultiplexed Bus, With Read/Write Delay, Normal ALE Data Sheet t ...
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ALE t 38 CSxL A23-A16 A15-A0 BHE CSxE Read Cycle BUS (D15-D8) D7-D0 RD RdCSx Write Cycle BUS (D15-D8) D7-D0 WR, WRL, WRH WrCSx Figure 20 External Memory Cycle: Demultiplexed Bus, With Read/Write Delay, Extended ALE ...
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ALE CSxL A23-A16 A15-A0 BHE, CSxE t Read Cycle BUS (D15-D8) D7-D0 RD RdCSx Write Cycle BUS (D15-D8) D7-D0 WR, WRL, WRH WrCSx Figure 21 External Memory Cycle: Demultiplexed Bus, No Read/Write Delay, Normal ALE Data Sheet t ...
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ALE t 38 CSxL A23-A16 A15-A0 BHE, CSxE t 6 Read Cycle BUS (D15-D8) D7-D0 RD RdCSx Write Cycle BUS (D15-D8) D7-D0 WR, WRL, WRH WrCSx Figure 22 External Memory Cycle: Demultiplexed Bus, No Read/Write Delay, Extended ALE ...
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Package Outlines 0.65 0.3 ±0. Index Marking 1) Does not include plastic or metal protrusion of 0.25 max. per side Figure 23 P-MQFP-80-7 (Plastic Metric Quad Flat Package) You can find all of our packages, sorts of ...
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