DP83952 National Semiconductor, DP83952 Datasheet
DP83952
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DP83952 Summary of contents
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... DP83950 RIC RIC II is fully backward pin and functional compatible with the RIC The DP83952 RIC II has the same basic architecture as the RIC with additional feature enhancements RIC II provides addi- tional network security options additional statistics for re- peater activities and a faster processor interface When RIC II is used in a ‘ ...
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... Manchester data an Elasticity Buffer for preamble regeneration transmit encoder and de- multiplexor for Manchester data The DP83952 RIC II can be connected cable seg- ments via its network interface ports One port is fully AUI compatible and is able to connect to an external MAU using ...
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Connection Diagrams Pin Name Pin No TXO12P b TXO12 a TXO12 b TXO12P a RXI12 b RXI12 GND RXI11 b RXI11 a TXO11P a TXO11 b TXO11 a TXO11P GND TXO10P ...
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Connection Diagrams DataSheet4U.com 4 DataSheet U .com (Continued) DataSheet4U.com Ports 2 – Port 1 AUI 12499– 2 ...
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Connection Diagrams Pin Name Pin No TXO12P b TXO12 a TXO12 b TXO12P a RXI12 b RXI12 GND RXI11 b RXI11 a TXO11P a TXO11 b TXO11 a TXO11P GND TXO10P ...
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Connection Diagrams DataSheet4U.com 4 DataSheet U .com (Continued) DataSheet4U.com Ports 6 – Ports 1 – 5 AUI 12499– 3 ...
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Connection Diagrams Pin Name Pin No TXO12P b TXO12 a TXO12 b TXO12P a RXI12 b RXI12 GND RXI11 b RXI11 a TXO11P a TXO11 b TXO11 a TXO11P GND TXO10P ...
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Connection Diagrams DataSheet4U.com 4 DataSheet U .com (Continued) DataSheet4U.com Ports 8 – Ports 1 – 7 AUI 12499– 4 ...
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Connection Diagrams Pin Name Pin No TX12 b TX12 a CD12 b CD12 a RX12 a RX12 GND RX11 a RX11 b CD11 a CD11 b TX11 a TX11 GND TX10 ...
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Connection Diagrams DataSheet4U.com 4 DataSheet U .com (Continued) DataSheet4U.com All AUI Ports 12499– 5 ...
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Pin Description Pin Name NETWORK INTERFACE PINS (On-Chip Transceiver Mode) RXI2 to RXI13 b b RXI2 to RXI13 a a TXOP2 to TXOP13 b TXO2 to TXO13 b TXO2 to TXO13 a TXOP2 to TXOP13 a CD1 ...
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Pin Description Driver Pin Name I O Type PROCESSOR BUS PINS RA0–RA4 TT I STR0 C O STR1 – BUFEN C O RDY C O ELI C O RTI C O ...
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Pin Description Driver Pin Name Type INTER-RIC BUS PINS ACKI TT ACKO TT IRD TT IRE TT IRC TT COLN TT PKEN C CLKIN TT ACTND OD ACTNS TT ANYXND OD ANYXNS TT TT TTL compatible B ...
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Pin Description Driver Pin Name I O Type MANAGEMENT BUS PINS MRXC MCRS MRXD MEN C O PCOMP TT I POWER AND GROUND PINS V CC GND EXTERNAL ...
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Block Diagram DataSheet4U.com 4 DataSheet U .com DataSheet4U.com 15 ...
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Block Diagram Note The block diagram for the RIC II when used in the non-secure mode is identical to the block diagram for the RIC device ( Figure 4-1 ) When RIC II is used in the ...
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... Pin Compatibility The DP83952VUL RIC II is fully pin compatible with the DP83950BVQB RIC device in the 160-pin Plastic Quad Flat Pack (PQFP) package 2 Addition of network security The DP83952 RIC II fea- tures significant per port security capability As a single chip repeater RIC II provides security using 58 internal ...
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Functional Description The main state machine is associated with a series of tim- ers These ensure various IEEE specification times (referred to as the TW1 to TW6 times) are fulfilled A repeater unit is required to meet ...
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... This is similar to the Inter-RIC bus since it allows the data packet to be recovered from the receiving RIC II Unlike the Inter-RIC bus the intended recipient is not another RIC II but National Semiconductor’s DP83932 ‘‘SONIC ’’ Network controller or the DP83957 RIB The ...
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Functional Description DataSheet4U.com 4 DataSheet U .com (Continued) DataSheet4U.com FIGURE 5-2 IEEE Repeater Main State Diagram 12499– 9 ...
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Functional Description PORT STATE MACHINE (PSM) There are two primary functions for the PSM as follows 1 Control the transmission of repeated data pseudo ran- dom data and jam signals over the attached segment 2 Decide whether ...
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Functional Description The following table briefly describes the operation of the Inter-RIC bus signals the conditions required for a RIC II to assert a signal and which RIC IIs (in a multi-RIC II system) would monitor the ...
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Functional Description METHODS OF RIC II CASCADING In order to build multi-RIC II repeaters PORT N and PORT M identification must be performed across all the RIC IIs in the system Inside each RIC II the PSMs ...
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Functional Description shows the functional timing diagram for this packet repeti- tion represented by the signals shown in Figure 5-3 In this example only two ports in the system are shown In non-se- cure mode the other ...
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Functional Description Note 1 The activity shown on RX DataSheet4U.com 4 DataSheet U .com (Continued) DataSheet4U.com represents the transmitted signal on TX after being looped back by the attached transceiver A1 A1 FIGURE 5-4 Data Repetition 25 ...
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Functional Description Note 1 SEND PREAMBLE SEND SFD SEND DATA DataSheet4U.com 4 DataSheet U .com (Continued) DataSheet4U.com FIGURE 5-5 Receive Collision 12499 – 12 ...
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Functional Description RECEIVE COLLISIONS A receive collision is a collision which occurs on the network segment attached to PORT ceived’’ similar manner as a data packet is received and then repeated to ...
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Functional Description Eventually the collision on port B1 ends and the ANYXN extension by the MSMs expires There is only one collision on the network (this may be deduced since ANYXN is inac- tive) so the repeater ...
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Functional Description Note 1 The IEEE Specification does not have a jabber protect state defined in its main state diagram this behavior is defined in an additional MAU Jabber Lockup Protection state diagram Note The Inter-RIC bus ...
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Functional Description Note DE Bus Drive Enable active high RE e Note The Inter-RIC bus is configured to use active low signals DataSheet4U.com 4 DataSheet U .com (Continued) Bus Receive Enable active low e FIGURE 5-8 External ...
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Functional Description 5 5 DESCRIPTION OF HARDWARE CONNECTION FOR INTER-RIC BUS When considering the hardware interface the Inter-RIC bus may be viewed as consisting of three groups of signals 1 Port Arbitration chain namely ACKI and ACKO ...
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Functional Description It is important to note that RIC II will learn the address of the packet if LME is set regardless of the D0 setting of MLOAD i e secure or non-secure mode It is also ...
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Functional Description Pin Programming Name Function RA0 BYPAS1 RA1 BYPAS2 RA2 BINV RA3 EXPLL RA4 resv DataSheet4U.com 4 DataSheet U .com (Continued) TABLE 5-1 Pin Definitions for Options in the Mode Load Operation (Continued) Effect When Effect ...
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Functional Description 5 7 DESCRIPTION OF HARDWARE CONNECTION FOR PROCESSOR AND DISPLAY INTERFACE DISPLAY UPDATE CYCLES The RIC II possesses control logic and interface pins which may be used to provide status information concerning activi ...
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Functional Description Signal Pin Name D0 No operation D1 Provides status information indicating if there is a collision occurring on one of the segments attached to this RIC II D2 Provides status information indicating if one of ...
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Functional Description DataSheet4U.com 4 DataSheet U .com (Continued) DataSheet4U.com 36 ...
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Functional Description 259 Output 259 Addr S2–0 RIC II Port Number RIC II D0 259 1 RIC II D1 259 2 RIC II D2 259 3 RIC II D3 259 4 RIC II D4 259 5 259 ...
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Functional Description DataSheet4U.com 4 DataSheet U .com (Continued) FIGURE 5-12 Processor Connection Diagram DataSheet4U.com 12499 –18 ...
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... An example of the processor and display interfaces is shown in Figure 5-12 INTERRUPT HANDLING The DP83952 RIC II offers an alternate method for a faster access to determine the source of the Event Logging Inter- rupt (ELI) then the DP83950 RIC For an event logging interrupt due to flag found the ...
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Hub Management Support Receive Collision (RXCOL) The receive collision flag for a port goes active when the port is the receive source of net- work activity and suffers a collision provided no other net- work segments experience ...
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Hub Management Support reset to zero and all count masks are forced into the dis- abled state Section 8 of the data sheet details the address location of the port event counters 6 2 EVENT RECORD FUNCTION ...
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Hub Management Support If the repeated packet ends before PCOMP is asserted or before the required number of bytes have been trans- ferred then the hub management status field is directly appended to the received data at ...
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Hub Management Support Packet Status Register (PSR) (Note 1) PSR(0) PSR(1) PSR(2) PSR(3) Collision Bit Timer PSR(4) Lower Repeat Byte Count PSR(5) Upper Repeat Byte Count PSR(6) Inter Frame Gap Bit Timer Note 1 These registers may ...
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Hub Management Support DataSheet4U.com 4 DataSheet U .com (Continued) DataSheet4U.com 44 ...
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Hub Management Support PACKET STATUS REGISTER Bit Symbol D0 resv D1 PCOMPD D(7 2) A(5 0) PACKET STATUS REGISTER CRCER FAE Bit Symbol D CLN ...
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Hub Management Support MODIFIED PACKET STATUS REGISTER 5 (MPS 1 IN GSR REGISTER) e RIC II provides an option for a new Packet Status Register 5 (PSR5) field On the seven bytes of management status field PSR5 ...
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Port Block Functions The RIC II has 13 port logic blocks (one for each network connection) In addition to the packet repetition operations already described the port block performs two other func- tions 1 the physical connection ...
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Port Block Functions Note For recommended modules see ‘‘Ethernet Magnetics Vendors for 10BASE-T 10BASE2 and BASE5’’ In this example Pulse Engineering’s PE-65438 device is used FIGURE 7-2 Port Connection to a 10-BASE2 Segment (AUI Interface Selected) The ...
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Port Block Functions 7 3 PORT STATUS REGISTER FUNCTIONS Each RIC II port has its own status register In addition to providing status concerning the port and its network seg- ment the register allows the following operations ...
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Port Block Functions 7 4 LOCAL PORTS AND INTER-RIC BUS EXPECTED ACTIVITY The RIC II incorporates security options into the repeater The configuration of the security features can be performed globally per port basis ...
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Port Block Functions 7 5 LOCAL PORTS AND INTER-RIC BUS DATA FIELD CONTENTS SME ESA Note SME Security Mode bit in the Port Security Configuration Register (PSCR) ESA Source Address Security bit ...
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RIC II Registers Address PAGE (0) 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H Device Type Register 12H Lower Event Count Mask Register (ECMR) 13H Upper ECMR ...
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RIC II Registers Address 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH Address 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH DataSheet4U.com 4 ...
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RIC II Registers Address 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH DataSheet4U.com 4 DataSheet U .com (Continued) Register Address Map (Continued) Name PAGE (13) PAGE (14) SCAM Lo 18 ...
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RIC II Registers Address D7 (Hex) 00 BINV DISPT 0E MINMAX 0F IVCTR3 10 FC Address D7 (Hex BDLNKC 13 resv 14 BDLNKE 15 res 16 IFC PCD7 ...
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RIC II Registers Address D7 (Hex EC7 1E res 1F ADV Address D7 (Hex PCAMx D7 13 res 14 ADV 15 16 PCAMx D7 17 res 18 ADV 19 1A PCAMx D7 ...
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RIC II Registers Address D7 (Hex) 11 res 12 ADV 13 14 PCAMx 15 res 16 ADV 17 18 PCAMx 19 res 1A ADV 1B 1C PCAMx 1D res 1E ADV 1F PCAMx Note For Port CAM ...
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RIC II Registers Register Array Bit Map Addresses 11H to 1FH Pages ( FH) Address D7 (Hex) 11 SCAMx PTR2 14 SCAMx PTR2 17 SCAMx ...
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RIC II Registers RIC II STATUS AND CONFIGURATION REGISTER (ADDRESS 00H) The lower portion of this register contains real time information concerning the operation of the RIC II The upper three bits represent the chosen configuration of ...
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... Note 2 This bit has no effect when external transceiver is selected Note 3 (for RIC II only) In addition to hysteresis that DP83950 RIC provides on normal receive squelch DP83952 RIC II provides a hysteresis when operating in the reduced squelch level mode DataSheet4U ...
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RIC II Registers RIC II CONFIGURATION REGISTER (ADDRESS 0EH) This register displays the state of a number of RIC II configuration bits loaded during the Mode Load operation D7 D6 MINMAX DPART Bit R W Symbol D0 ...
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RIC II Registers REAL TIME INTERRUPT REGISTER (ADDRESS 0FH) The Real Time Interrupt register (RTI) contains information which may change on a packet by packet basis Any remaining interrupts which have not been serviced before the following ...
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... LOW COUNT This indicates one of the port event counters has a value less than 00FF Hex HC HIGH COUNT This indicates one of the port event counters has a value greater than C000 Hex FC FULL COUNTER This indicates one of the port event counters has a value equal to FFFF Hex DataSheet4U.com 63 Description 1 for the DP83952 RIC II device ...
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RIC II Registers LOWER EVENT COUNT MASK REGISTER (PAGE 0H ADDRESS 12H BDLNKC PARTC RECC Bit R W Symbol JABC JABBER COUNT ENABLE Enables recording of Jabber Protect events D1 R ...
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RIC II Registers EVENT RECORD MASK REGISTER (PAGE 0H ADDRESS 14H BDLNKE PARTE Bit R W Symbol JABE ELBERE PLERE NSFDE D4 R ...
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RIC II Registers INTERRUPT AND MANAGEMENT CONFIGURATION REGISTER (PAGE 0H ADDRESS 16H) This register powers up with all bits set to one and must be initialized by a processor write cycle before any events will generate interrupts ...
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RIC II Registers RIC II ADDRESS REGISTER (PAGE 0H ADDRESS 17H) This register may be used to differentiate between RIC IIs in a multi-RIC II repeater system The contents of this register form part of the information ...
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RIC II Registers INTER FRAME GAP THRESHOLD SELECT REGISTER (PAGE 0H ADDRESS 1FH) This register is used to configure the hub management interface to provide a certain minimum inter frame gap between packets transmitted over the management ...
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RIC II Registers UPPER EVENT INFORMATION REGISTER (UPPER EIR) (PAGE 1H ADDRESS 1EH ER8 ER7 Bit R W Symbol D0 R ER1 D1 R ER2 D2 R ER3 D3 R ER4 D4 R ER5 D5 ...
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RIC II Registers PORT EVENT COUNT REGISTER (PAGES 2H AND 3H) The Event Count (EC) register shows the instantaneous value of the specified port’s 16-bit counter The counter increments when an enabled event occurs The counter may ...
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RIC II Registers PORT SECURITY CONFIGURATION REGISTER (PSCR) (PAGES 9H) This register sets up the various security modes for the RIC II It provides port specific information such as enabling disabling the security ...
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RIC II Registers PORT CAM POINTER REGISTER (PCPR) (PAGES 9H) This register indicates which bytes of the six Ethernet address bytes has been stored in the CAM locations When a byte has been ...
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RIC II Registers SHARED CAM VALIDATION REGISTER 1 (SCVR 1) (PAGE 9H ADDRESS 16H) This register indicates the validity of an Ethernet address stored in any one of the shared CAMs When a ‘‘1’’ is written in ...
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RIC II Registers SHARED CAM VALIDATION REGISTER 2 (SCVR 2) (PAGE 9H ADDRESS 17H) This register indicates the validity of an Ethernet address stored in any one of the shared CAMs When a ‘‘1’’ is written in ...
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RIC II Registers SHARED CAM VALIDATION REGISTER 3 (SCVR 3) (PAGE 9H ADDRESS 18H) This register indicates the validity of an Ethernet address stored in any one of the shared CAMs When a ‘‘1’’ is written in ...
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RIC II Registers SHARED CAM VALIDATION REGISTER 4 (SCVR 4) (PAGE 9H ADDRESS 19H) This register indicates the validity of an Ethernet address stored in any one of the shared CAMs When a ‘‘1’’ is written in ...
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RIC II Registers SHARED CAM REGISTER (PAGES FH) This register accesses the 48 bits of the shared CAM address Six write read cycles are required to load read the entire 48-bit ...
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RIC II Registers CAM LOCATION MASK REGISTER (CLMR) (PAGES FH) Each shared CAM has a CLMR therefore there are 32 CLMRs Any of the 32 CAMs can be shared among the ...
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... AC and DC Specifications Absolute Maximum Ratings If Military Aerospace specified devices are required please contact the National Semiconductor Sales Office Distributors for availability and specifications Supply Voltage ( Input Voltage ( Output Voltage (V DC Specifications Symbol PROCESSOR LED TWISTED PAIR PORTS INTER-RIC AND MANAGEMENT INTERFACES ...
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Timing and Load Diagrams PORT ARBITRATION TIMING Number Symbol T1 ackilackol T2 ackihackoh Note Timing valid with no receive or collision activities Note In these diagrams the Inter-RIC and Management Busses are shown using active high signals ...
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Timing and Load Diagrams TRANSMIT TIMING AUI PORTS Transmit activity propagation start up and end delays for ports in non 10BASE-T mode Number T15a Note ACKI assumed high TRANSMIT TIMING 10BASE-T PORTS Receive activity propagation start up ...
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Timing and Load Diagrams RECEIVE COLLISION TIMING Number Symbol T32a cdacolna T33a cdicolni T39 colnajs T40 colnije Note 1 PKEN assumed high Note 2 Assuming reception ended before COLN goes inactive TW2 is included in this parameter ...
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Timing and Load Diagrams COLLISION TIMING AUI PORTS Number T34 T35 T38 Number Symbol T36 actnitxi T37 anyitxoi DataSheet4U.com 4 DataSheet U .com (Continued) Symbol Parameter anyamin ANYXN Active Time anyitxai ANYXN Inactive all ...
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Timing and Load Diagrams INTER RIC BUS OUTPUT TIMING Number Symbol T101 ircoh T102 ircol T103 ircoc T104 actndapkena T105 actndairea T106 ireairca T107 irdov T108 irdos T109 ircohirei T110 ircclks INTER RIC BUS INPUT TIMING Number ...
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Timing and Load Diagrams MANAGEMENT BUS TIMING Number T50 mrxch T51 mrxcl T52 mrxcd T53 actndamena T54 actndamcrsa T55 mrxds T56 mrxdh T57 mrxclmcrsi T58 mcrsimenl T59 mrxcclks T60 pcompw Note The preamble on this bus consists ...
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Timing and Load Diagrams MLOAD TIMING Number Symbol T61 mldats T62 mldath T63 mlabufa T64 mlibufi T65 mlw STROBE TIMING Number Symbol T66 stradrs T67 strdats T68 strdath T69 strw CDEC TIMING Number Symbol T70 cdecpw T71 ...
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Timing and Load Diagrams REGISTER READ TIMING Number T80 T81 T82 T83 T84 T85 T86 T87 T88 Note Minimum high time between read write cycles is 100 ns DataSheet4U.com 4 DataSheet U .com (Continued) Symbol Parameter rdadrs ...
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Timing and Load Diagrams REGISTER WRITE TIMING Number T90 T91 T92 T93 T94 T95 T96 T97 T98 T99 Note Assuming zero propagation delay on external buffer Note Minimum high time between read write cycles is 100 ns ...
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AC Timing Test Conditions All specifications are valid only if the mandatory isolation is employed and all differential signals are taken the AUI side of the pulse transformer Input Pulse Levels (TTL CMOS) Input ...
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