DP83843 National Semiconductor, DP83843 Datasheet
DP83843
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DP83843 Summary of contents
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... DP83843BVJE PHYTER General Description The DP83843BVJE is a full feature Physical Layer device with integrated PMD sublayers to support both 10BASE-T and 100BASE-X Ethernet protocols. This VLSI device is designed for easy implementation of 10/100 Mb/s Ethernet LANs. It interfaces directly to Twisted Pair media through an external transformer or to fiber media via industry standard electrical/optical fi ...
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Block Diagram HARDWARE CONFIGURATION PINS (REPEATER, SERIAL10, SYMBOL, , AN0, AN1,FXEN PHYAD[4:0]) TX_DATA TX_DATA TRANSMIT CHANNELS & STATE MACHINES 100 MB/S 10 MB/S 4B/5B ENCODER NRZ TO MANCHESTER SCRAMBLER ENCODER PARALLEL TO SERIAL LINK PULSE GENERATOR NRZ TO NRZI ENCODER ...
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... Reference Clock Connection Options . . . . . . . . . 36 5.0 Reset Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 5.1 Power-up / Reset . . . . . . . . . . . . . . . . . . . . . . . . . 37 5.2 Hardware Reset . . . . . . . . . . . . . . . . . . . . . . . . . . 37 5.3 Software Reset . . . . . . . . . . . . . . . . . . . . . . . . . . 37 6.0 DP83843 Application . . . . . . . . . . . . . . . . . . . . . . . . . . 38 6.1 Typical Node Application . . . . . . . . . . . . . . . . . . . 38 6.2 Power And Ground Filtering . . . . . . . . . . . . . . . . 38 6.3 Power Plane Considerations . . . . . . . . . . . . . . . . 38 7.0 User Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 7.1 Link LED While in Force 100Mb/s Good Link . . . 42 7 ...
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... TPRD+ 67 TW_AVDD 68 SERIAL10 69 SUB_GND1 70 CD_GND0 71 CD_VDD0 72 TPTD- 73 TPTD+ 74 CD_GND1 75 CD_VDD1 76 SUB_GND2 77 TXAR100 78 TR_AVDD 79 TR_AGND DP83843BVJE PHYTER Order Number DP83843BVJE NS Package Number VJE80 4 40 LED_RX/PHYAD[2] 39 LED_LINK/PHYAD[3] 38 LED_FDPOL/PHYAD[4] 37 IO_VSS5 36 IO_VDD5 35 MDC 34 MDIO 33 TX_CLK 32 IO_VSS4 31 TXD[0] 30 TXD[1] 29 TXD[2] 28 TXD[3] 27 IO_VSS3 26 IO_VDD3 25 TX_EN 24 TX_ER 23 RX_EN ...
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... Pin Descriptions The DP83843 pins are classified into the following interface categories. Each interface is described in the sections that follow. — MII INTERFACE — 10/100 Mb/s PMD INTERFACE — CLOCK INTERFACE 1.1 MII Interface Signal Name Type Pin # MDC I 35 MANAGEMENT DATA CLOCK: Synchronous clock to the MDIO management data in- put/output serial interface which may be asynchronous to transmit and receive clocks ...
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... Link Pulses (including Fast Link Pulses for Auto-Negotiation pur- poses.) 100BASE-TX: Reception of ANSI X3T12 compliant scrambled MLT-3 data. The DP83843 will automatically configure this common input buffer to accept the proper signal type as a result of either forced configuration or Auto-Nego- tiation. 100BASE- Mb/s AUI TRANSMIT DATA: This configurable output driver supports either 125 Mb/s PECL, for 100BASE-FX applications Mb/s AUI signaling ...
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... While the value of the resistor should be evaluated on a case by case bases, the DP83843 was designed to produce an amplitude close to the re- quired range of 2V pk-pk differential driving a typical 100 differential load without a resistor connected to this pin. ...
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... Description CRYSTAL/OSCILLATOR INPUT: This pin is the primary clock reference input for the DP83843 and must be connected MHz 0.005% (50 ppm) clock source. The DP83843 device supports either an external crystal resonator connected across pins X1 and X2 external CMOS-level oscillator source connected to pin X1 only. For 100 Mb/s repeater applications, X1 should be tied to the common 25 MHz transmit clock reference ...
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... MHz clock rate on the least signifi- cant bits of the nibble-wide MII data buses, pins TXD[0] and RXD[0] respectively. This mode is intended for use with the DP83843 connected to a MAC using a 10 Mb/s serial interface. Serial operation is not supported in 100 Mb/s mode, therefore this input is ignored during 100 Mb/s operation ...
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... LED_LINK. LED_LINK will deassert in accordance with the Link Loss Timer as specified in IEEE 802.3. In 100BASE-FX mode, link is established as a result of the assertion of the Signal detect input to the DP83843. LED_LINK will assert after Signal Detect has remained asserted for a minimum of 500 S. LED_LINK will deassert immediately following the deassertion of signal detect. ...
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... Description RESET: Active high input that initializes or reinitializes the DP83843. Asserting this pin will force a reset process to occur which will result in all internal registers reini- tializing to their default states as specified for each bit in section 7.0, and all strap- ping options are reinitialized ...
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... Pin Descriptions (Continued) 1.8 Power And Ground Pins The power (V ) and ground (GND) pins of the DP83843 CC are grouped in pairs into three categories--TTL/CMOS Input pairs, Transmit/Receive supply pairs, and Internal Signal Name Pin # TTL/CMOS INPUT/OUTPUT SUPPLY PAIRS IO_VDD1 6 IO_VSS1 7 IO_VDD2 ...
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... MDIO signal during the first bit of Turnaround during a read transaction. The addressed DP83843 drives the MDIO with a zero for the second bit of turnaround and follows this with the required data. Figure 2 shows the timing relationship between MDC and the MDIO as driven/received by the Station Management Entity and the DP83843 (PHY) for a typical register read access ...
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... PHY Address is set to 00000 upon power-up/hard- ware reset. Otherwise, the DP83843 will set this bit to zero upon power-up/hardware reset. With bit 10 in the BMCR set to one, the DP83843 does not respond to packet data present at TXD[3:0], TX_EN, and TX_ER inputs and presents a high impedance on the TX_CLK, RX_CLK, RX_DV, RX_ER, RXD[3:0], COL, and CRS outputs ...
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... The bypass option for the functional blocks within the 100BASE-X transmitter provides flexibility for applications such as 100 Mb/s repeaters where data conversion is not always required. The DP83843 implements the 100BASE- X transmit state machine diagram as specified in the IEEE 802.3u Standard, Clause 24. ...
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... LBR (address 17h). It should be noted that if the scrambler is bypassed by forcing the FXEN pin (and subse- quently resetting the device) the TPTD become disabled and the test pattern data will be routed to the FXTD/AUITD outputs. Additionally, the test patterns will not be generated if the DP83843 is in symbol mode binary_in (Continued) 2 ...
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Functional Description Table 2. 4B5B Code-Group Encoding/Decoding Name PCS 5B Code-group DATA CODES IDLE AND CONTROL CODES ...
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... While signal detect is normally generated and processed entirely within the DP83843, it can be observed directly on the CRS pin (pin 22) while the DP83843 is configured for Symbol mode. Refer to Section 3.4 for further detail regard- ing Symbol mode operation. 2.3.3 Digital Adaptive Equalization ...
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Functional Description RX_CLK CARRIER INTEGRITY MONITOR LINK INTEG- RITY MONITOR RX_DATA VALID SSD DETECT CLOCK CLOCK RECOVERY MODULE (Continued) RXD[3:0] / RX_ER BP_RX MUX MUX BP_4B5B 4B/5B DECODER CODE GROUP ALIGNMENT MUX BP_SCR DESCRAMBLER SERIAL TO PARALLEL NRZI TO ...
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... The CRM is implemented using an advanced digital Phase Locked Loop (PLL) architecture that replaces sensitive analog circuits. Using digital PLL circuitry allows the DP83843 to be manufactured and specified to tighter toler- ances. For further information relating to the 100BASE-X clock recovery module, refer to Section 4.3. ...
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Functional Description 2ns/div Figure 1. MLT-3 Signal Measured at AII after 50 meters of CAT-5 cable 2ns/div Figure 2. MLT-3 Signal Measured at AII after 100 meters of CAT-5 cable 2.3.6 NRZI to NRZ In a typical application, the ...
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... Operational Modes The DP83843 has 2 basic 10BASE-T operational modes: Half Duplex mode Full Duplex mode Half Duplex Mode In Half Duplex mode the DP83843 functions as a standard IEEE 802.3 CSMA/CD protocol. Full Duplex Mode In Full Duplex mode the DP83843 is capable of simulta- neously transmitting and receiving without asserting the collision signal ...
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... The Jabber function is only meaningful in 10BASE-T mode. 2.4.7 Status Information 10BASE-T Status Information is available on the LED out- put pins of the DP83843. Transmit activity, receive activity, link status, link polarity and collision activity information is output to the five LED output pins (LED_RX, LED_TX, LED_LINK, LED_FDPOL, and LED_COL) ...
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... Chapter 26 of the IEEE 802.3u specification defines the interface to this PMD sublayer. The DP83843 can be configured for 100BASE-FX opera- tion either through hardware or software. Configuration through hardware is accomplished by forcing the FXEN pin (pin 21 logic low level prior to power-up/reset. Confi ...
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... FXSD pins. If three or more FEFI IDLE patterns are detected by the DP83843, then bit 4 of the Basic Mode Status register (address 01h) is set to one until read by management also set in bit 7 of the PHY Status register (address 10h). The first FEFI IDLE pattern may contain more than 84 ones as the pattern may have started during a normal IDLE transmission which is actually quite likely ...
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... Functional Description LBR(17h)) and disable Auto-Negotiation. Without FEFI enabled the DP83843 will not send the FEFI idle pattern. Additionally, upon detection of Far End Fault, all receive and transmit MII activity is disabled/ignored (MII serial management is unaffected). DP83843 100BASE-FX 50 FXRD +/- 49 48 FXSD ...
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... AUI and TP operation. The AUI/TPI autoswitch feature (AUTOSW_EN) is enabled by bit 9 of the 10BASE-T Control and Status Register (10BTSCR). If AUTOSW_EN is asserted (default is de-asserted) and the DP83843 Mb/s mode it automatically activates the TPI interface (10 Mb/s data is transmitted and received at the TPTD and TPRD pins respectively) ...
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... AN0 and AN1 pins. The BMCR provides software with a mechanism to control the operation of the DP83843. However, the AN0 and AN1 pins do not affect the contents of the BMCR and cannot be used by software to obtain status of the mode selected.Bits 1 & ...
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... Extended Register Capability (bit 0, register address 01h). These bits are per- manently set to indicate the full functionality of the DP83843 (only the 100BASE-T4 bit is not set since the DP83843 does not support that function, while it does sup- port all the other functions). ...
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... LED output pins as: LED_COL <=> PHYAD[0] LED_TX <=> PHYAD[1] LED_RX <=> PHYAD[2] LED_LINK <=> PHYAD[3] LED_FDPOL <=> PHYAD[4] The DP83843 can be set to respond to any of 32 possible PHY addresses. Each DP83843 connected to a common serial MII must have a unique address. It should be noted 30 after the ...
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... LED operations and configu- ration. 3.3 Half Duplex vs. Full Duplex The DP83843 supports both half and full duplex operation at both 10 Mb/s and 100 Mb/s speeds. Half-duplex is the standard, traditional mode of operation which relies on the CSMA/CD protocol to handle collisions and network access ...
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... PMD, clock recovery, and clock generation functions of the DP83843. This is accomplished either by configuring the CRS/SYM- BOL pin (pin 22) of the DP83843 to a logic low level prior to power-up/reset or by setting bits 10 and 11 (BP_TX and BP_RX respectively) of the LBR register (address 17h) through the serial MII port ...
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... Refer to Section 2.4.2 for infor- mation relating to the requirements for selecting a given PHYAD. With bit 10 in the BMCR set to one the DP83843 does not respond to packet data present at TXD[3:0], TX_EN, and TX_ER inputs and presents a high impedance on the TX_CLK, RX_CLK, RX_DV, RX_ER, RXD[3:0], COL, and CRS outputs ...
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... As depicted in Figure 17, the single 25 MHz reference serves both the 100 Mb/s and 10 Mb/s mode clocking requirements. The DP83843 also incorporates Clock Recovery circuitry (CRM) which extracts the 125 MHz clock from the 125 Mb/s receive datastream present during 100BASE-TX and 100BASE-FX applications (Figure 17) ...
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Clock Architecture (Continued) 125Mb/s Phase Serial Data Detector Input Divide by 2 Frequency Reference From CGM Figure 18. 100BASE-X Clock Recovery Module block diagram 10 Mb/s Phase Serial Data Detector Input & CRS Figure 19. 10M Manchester Clock Recovery ...
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... Mb/s datastream, Carrier Sense (CRS) is gen- erated for use by the MAC. 4.4 Reference Clock Connection Options The two basic options for connecting the DP83843 to an external reference clock consist of the use of either an oscillator or a crystal. Figure 20 and 21 illustrate the rec- ommended connection for the two typical options ...
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... DP83843 (see list below) are also latched into the device as a function of the reset operation (either hardware or software). These hardware configura- tion values are guaranteed to be latched into the DP83843 2 s after the deassertion of the RESET pin. The hardware configuration values latched into the ...
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... Power Plane Considerations The recommendations for power plane considerations pro- 6.2 Power And Ground Filtering Sufficient filtering between the DP83843 power and ground pins placed as near to these pins as possible is recom- mended. Figure 23 suggests one option for device noise fil- tering including special consideration for the sensitive analog power pins ...
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... ALL CAPS ARE 16V CERAMIC = FERRITE BEAD TDK # HF70ACB-321611T 26 AT 100MHZ Figure 23. Power and Ground Filtering for the DP83843 By placing chassis ground on the top and bottom layers, additional EMI shielding is created around the 125Mb/s sig- nal traces that must be routed between the magnetics and the RJ45-8 media connector ...
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... Ground Plane: Chassis Layer 2 Ground Plane: System Ground Layer Planes: System V CC Layer 4 (bottom) Ground Plane: Chassis Figure 24. Typical plane layout recommendation for DP83843 Signal Routing Magnetics DP83843 System Ground DP83843 Magnetics System Ground System V CC DP83843 Magnetics System V CC Signal Routing ...
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... DP83843 10/100 TX RX Figure 25. Typical DP83843 Network Interface with additional ESD protection For applications where high reliability is required rec- ommended that additional ESD protection diodes be added as shown below. There are numerous dual series con- nected diode pairs that are available specifically for ESD protection ...
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... Solution not recommended that the DP83843BVJE be used for AUI repeater applications where the transmit data is looped back to the receive channel at the transceiver. (i.e. CTI). Additionally, 10M serial and nibble repeater applications are not currently directly supported ...
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... Note that the board layout, the magnetics, and the output signal of the DP83843BVJE each contribute to the final rise and fall times as measured across the RJ45-8 transmit pins. It should be noted that excessive capacitive loading across the TPTD+/- pins may result in improper transmit return loss performance at high frequencies (up to 80MHz) ...
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... If you want to run AutoNegotiation again, with reduced capabilities or all capabilities: Turn off AutoNegotiation by writing a 0000h to Register 0. (Need to do this to clear the DP83843 from sending idles.) Change the capabilities to the desired configuration by writ- ing to Register 4 (0061 for full10/half10, or 0021 for half10 only, etc ...
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Register Block 8.1 Register Definitions Register maps and address definitions are given in the following tables: Table 5. Register Block - Phyter Register Map Offset Access 00h RW BMCR 01h RO BMSR 02h RO PHYIDR1 03h RO PHYIDR2 04h ...
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Register Block (Continued) Table 6. Basic Mode Control Register (BMCR) Address 00h Bit Bit Name 15 Reset 14 Loopback 13 Speed Selection 12 Auto-Negotiation En- able 11 Power Down Default 0, RW/SC Reset Initiate software Reset / ...
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... Duplex Default Strap, RW Isolate Isolates the DP83843 from the MII with the exception of the serial management. When this bit is asserted, the DP83843 does not respond to TXD[3:0], TX_EN, and TX_ER inputs, and it pre- sents a high impedance on its TX_CLK, RX_CLK, RX_DV, RX_ER, RXD[3:0], COL and CRS outputs. ...
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Register Block (Continued) Table 7. Basic Mode Status Register (BMSR) Address 01h Bit Bit Name 12 10BASE-T Full Du- plex 11 10BASE-T Half Du- plex 10:7 Reserved 6 Preamble Suppression 5 Auto-Negotiation Complete 4 Remote Fault 3 Auto-Negotiation Ability ...
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... Register Block (Continued) The PHY Identifier Registers #1 and #2 together form a unique identifier for the DP83843. The Identifier consists of a concatenation of the Organizationally Unique Identifier (OUI), the vendor's model number and the model revision num- ber. A PHY may return a value of zero in each of the 32 bits of the PHY Identifier if desired. The PHY Identifier is intended to support network management. National's IEEE assigned OUI is 080017h. Table 8. PHY Identifi ...
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Register Block (Continued) Table 10. Auto-Negotiation Advertisement Register (ANAR) Address 04h Bit Bit Name 10_FD 5 10 4:0 Selector Advertised abilities of the Link Partner as received during Auto-Negotiation. Table 11. Auto-Negotiation Link Partner Ability Register ...
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Register Block (Continued) Table 11. Auto-Negotiation Link Partner Ability Register (ANLPAR) Address 05h Bit Bit Name 6 10_FD 5 10 4:0 Selector Default 0, RO 10BASE-T Full Duplex Support 10BASE-T Full Duplex is supported by the Link ...
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Register Block (Continued) Table 11. Auto-Negotiation Link Partner Ability Register (ANLPAR) Address 05h Bit Bit Name This register also contains the Link Partner Next Page contents ACK ACK2 11 TOGGLE 10:0 CODE Table ...
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Register Block (Continued) This register contains the next page information sent by this device to its Link Partner during Auto-Negotiation. Table 13. Auto-Negotiation Next Page Transmit Register (ANNPTR) Address 07h Bit Bit Name Reserved 13 MP ...
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Register Block (Continued) This register provides a single location within the register set for quick access to commonly accessed information. Table 14. PHY Status Register (PHYSTS) Address 10h Bit Bit Name 15 Receive Error Latch 14 CIM Latch 13 ...
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Register Block (Continued) Table 14. PHY Status Register (PHYSTS) Address 10h Bit Bit Name 3 Loopback Status 2 Duplex Status 1 Speed Status 0 Link Status This register implements the MII Interrupt PHY Specific Control register. Sources for interrupt ...
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Register Block (Continued) This counter provides information required to implement the isolates attribute within the Repeater Port managed object class of Clause 30 of the IEEE 802.3 specification. Table 17. Disconnect Counter Register (DCR) Address 13h Bit Bit Name ...
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Register Block (Continued) Table 20. 100 Mb/s PCS Configuration and Status Register (PCSR) Address 16h (Continued) Bit Bit Name 12 DESCR_TO_SEL 11 DESCR_TO_DIS 10 LD_SCR_SD 9 TX_QUIET 8:7 TX_PATTERN[1:0] 6 F_LINK_100 5 CIM_DIS Default 0, RW Descrambler Time-out Select: ...
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Register Block (Continued) Table 20. 100 Mb/s PCS Configuration and Status Register (PCSR) Address 16h (Continued) Bit Bit Name 4 CIM_STATUS 3 CODE_ERR 2 PME_ERR 1 LINK_ERR 0 PKT_ERR Table 21. Loopback & Bypass Register (LBR) Address 17h Bit ...
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Register Block (Continued) Table 21. Loopback & Bypass Register (LBR) Address 17h (Continued) Bit Bit Name 12 BP_SCR 11 BP_RX 10 BP_TX 9:7 100_DP_CTL 6 RESERVED 5 TW_LBEN 4 10Mb_ENDEC_LB 3 RESERVED 2 RESERVED Default Strap, RW Bypass Scrambler/Descrambler ...
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Register Block (Continued) Table 21. Loopback & Bypass Register (LBR) Address 17h (Continued) Bit Bit Name 1 RESERVED 0 RESERVED Table 22. 10BASE-T Control & Status Register (10BTSCR) Address 18h Bit Bit Name 15:14 RESERVED 13 AUI_TPI 12 RX_SERIAL ...
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Register Block (Continued) Table 22. 10BASE-T Control & Status Register (10BTSCR) Address 18h (Continued) Bit Bit Name 6 LS_SEL 5 AUI_SEL 4 JAB_DS 3 THIN_SEL 2 RX_FILT_DS 1 RESERVED 0 RESERVED Table 23. PHY Control Register (PHYCTRL) Address 19h ...
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Register Block (Continued) Table 23. PHY Control Register (PHYCTRL) Address 19h (Continued) Bit Bit Name 9 REPEATER 8:7 LED_TXRX_MODE 6 LED_DUP_MODE 5 FX_EN 4:0 PHYADDR[4:0] Default Strap, RW Repeater/Node Mode Repeater mode 0 = Node mode In ...
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... ECL Signal Output Current ESD Protection All preliminary electrical specifications are based on IEEE 802.3u requirements and internal design considerations. These specifications will not become final until complete verification of the DP83843. Thermal Characteristics* Maximum Case Temperature Maximum Die Temperature ...
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Electrical Specifications 9.1 DC Electrical Specification Symbol Pin Types Parameter V I Input High Voltage IH I/O I/O, Z AN0 and AN1 Input Low Voltage IL I/O I/O, Z AN0 and AN1 X1 V AN0 and ...
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Electrical Specifications Symbol Pin Types Parameter C O CMOS Output OUT1 Z Capacitance C O PECL Output OUT2 Z Capacitance SD TPRD 100BASE-TX THon Signal detect turn- on thresh SD TPRD 100BASE-TX THoff Signal detect turn- off thresh V ...
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Electrical Specifications 9.2 CGM Clock Timing X1 IN TX_CLK OUT T2.0.1 Parameter Description T2.0 TX_CLK Delay T2.0.2 TX_CLK Duty Cycle 9.3 MII Serial Management AC Timing MDC MDIO (OUTPUT) MDC MDIO (INPUT) Parameter Description T3.0.1 MDC to ...
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Electrical Specifications 9.4 100 Mb/s AC Timing 9.4.1 100 Mb/s MII Transmit Timing TX_CLK TXD[3:0] TX_EN TX_ER Parameter Description T4.1.1 TXD[3:0], TX_EN, TX_ER Data Setup to TX_CLK TXD[4:0] Data Setup to TX_CLK T4.1.2 TXD[3:0], TX_EN, TX_ER Data Hold from ...
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Electrical Specifications 9.4.3 100BASE-TX Transmit Packet Latency Timing TX_CLK TX_EN TXD TPTD+/- Parameter Description T4.3.1 TX_CLK to TPTD Latency Note: For Normal mode, latency is determined by measuring the time from the first rising edge of TX_CLK occurring after ...
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Electrical Specifications 9.4.4 100BASE-TX Transmit Packet Deassertion Timing TX_CLK TXD TX_EN TPTD+/- Parameter Description T4.4.1 TX_CLK to TPTD Deassertion Note: Deassertion is determined by measuring the time from the first rising edge of TX_CLK occurring after the deassertion of ...
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Electrical Specifications 9.4.5 100BASE-TX Transmit Timing TPTD+/- T4.5.2 TPTD+/- EYE PATTERN Parameter Description T4.5.1 100 Mb/s TPTD Rise and Fall Times 100 Mb/s Rise/Fall Mismatch T4.5.2 100 Mb/s TPTD Transmit Jitter Note: Normal Mismatch is the difference between the ...
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Electrical Specifications 9.4.6 100BASE-TX Receive Packet Latency Timing IDLE TPRD+/- CRS RXD[3:0] RX_DV RX_ER/RXD[4] Parameter Description T4.6.1 Carrier Sense on Delay T4.6.2 Receive Data Latency Note: Carrier Sense On Delay is determined by measuring the time from the first ...
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Electrical Specifications 9.4.8 100BASE-FX Transmit Packet Latency Timing TX_CLK TX_EN TXD FXTD+/- Parameter Description T4.8.1 TX_CLK to FXTD Latency Note: For Normal mode, Latency is determined by measuring the time from the first rising edge of TX_CLK occurring after ...
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Electrical Specifications 9.4.9 100BASE-FX Transmit Packet Deassertion Timing TX_CLK TXD TX_EN FXTD+/- Parameter Description T4.9.1 TX_CLK to FXTD Deassertion Note: Deassertion is determined by measuring the time from the first rising edge of TX_CLK occurring after the deassertion of ...
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Electrical Specifications 9.4.11 100BASE-FX Receive Packet Deassertion Timing FXRD+/- DATA CRS RXD[3:0] RX_DV RX_ER/RXD[4] Parameter Description T4.11.1 Carrier Sense Off Delay Note: Carrier Sense Off Delay is determined by measuring the time from the first bit of the “T” ...
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Electrical Specifications 9.5.13 10 Mb/s MII Receive Timing RX_EN T5.13.1 RX_CLK T5.13.3 RXD[3:0] RX_DV RX_ER Parameter Description T5.13.1 RX_EN to RX_CLK, RXD[3:0], RX_DV Active All 10 Mb/s modes T5.13.2 RX_EN to RX_CLK, RXD[3:0], RX_DV TRI- STATE T5.13.3 RX_CLK to ...
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Electrical Specifications 9.5.15 10BASE-T Transmit Timing (End of Packet) TX_CLK TX_EN TPTD+/- TPTD+/- Parameter Description T5.15.1 Transmit Enable Hold Time from the Rising Edge of TX_CLK T5.15.2 End of Packet High Time (with ‘0’ ending bit) T5.15.3 End of ...
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Electrical Specifications 9.5.16 10BASE-T Receive Timing (Start of Packet) TPRD+/- CRS RX_CLK RXD RX_DV Parameter Description T5.16.1 Carrier Sense Turn On Delay (TPRD to CRS) T5.16.2 Decoder Acquisition Time T5.16.3 Receive Data Latency T5.16.4 SFD Propagation Delay Note: 10BASE-T ...
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Electrical Specifications 9.5.18 10 Mb/s AUI Timing 1 AUITD+/- AUIRD+/- Parameter Description T5.18.1 AUI Transmit Output High Before Idle T5.18.2 AUI Transmit Output Idle Time T5.18.3 AUI Receive End of Packet Hold Time Note: The worst case for T5.18.1 ...
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Electrical Specifications 9.5.20 10 Mb/s Jabber Timing TXE TPTD+/- COL Parameter Description T5.20.1 Jabber Activation Time T5.20.2 Jabber Deactivation Time 9.5.21 10BASE-T Normal Link Pulse Timing Parameter Description T5.21.1 Pulse Width T5.21.2 Pulse Period Note: These specifications represent both ...
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Electrical Specifications 9.6 Auto-Negotiation Fast Link Pulse (FLP) Timing T6.21.1 FAST LINK PULSE(S) T6.21.4 Parameter Description T6.21.1 Clock, Data Pulse Width T6.21.2 Clock Pulse to Clock Pulse Period T6.21.3 Clock Pulse to Data Pulse Period T6.21.4 Number of Pulses ...
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Electrical Specifications 9.7.22 100BASE-X CRM Acquisition Time FXSD+ OR SD+ INTERNAL FXRD+/- Parameter Description T7.22.1 CRM Acquisition Note: The Clock Generation Module (CGM) must be stable for at least 100 s before the Clock Recovery Module (CRM) can lock ...
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Electrical Specifications 9.8 Reset Timing VCC HARDWARE RESET (OPTION #1) HARDWARE RESET (OPTION #2) MDC LATCH-IN OF HARDWARE CONFIGURATION PINS DUAL FUNCTION PINS BECOME ENABLED AS OUTPUTS Parameter Description T8.23.1 Internal Reset Time T8.23.2 Hardware RESET Pulse Width T8.23.3 ...
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Electrical Specifications 9.9 Loopback Timing TX_CLK TX_EN TXD[3:0] CRS RX_CLK RX_DV RXD[3:0] Parameter Description T9.23.1 TX_EN to RX_DV Loopback Note: Due to the nature of the descrambler function, all 100BASE-X Loopback modes will cause an initial “dead-time” ...
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Electrical Specifications 9.10 Isolation Timing CLEAR BIT 10 OF BMCR (RETURN TO NORMAL OPERATION FROM ISOLATE MODE) H/W OR S/W RESET (WITH PHYAD 00000) MODE Parameter Description T10.23.1 From software clear of bit 10 in the BMCR register to ...
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... IEEE 802.3u spec- ification. 10.6 Idd Measurement Conditions The DP83843 PHYTER is currently tested for total device Idd under four operational modes: — 100BASE-TX Full Duplex (max packet length / min IPG) for testing — ...
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... Test Conditions (Continued) DP83843 PHYTER DP83843 PHYTER DP83843 PHYTER Figure 29. 10/100 Twisted Pair Load (zero meters) AUITD/FXTD+ AUITD/FXTD- 50 VTT VTT Figure 27. 100BASE-FX Test Load V CC CMOS OUTPUT CURRENT SINK GND Figure 28. CMOS Output Test Load TPTD+ 100 TPTD- 10/100 AC COUPLING ...
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... National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications. inches (millimeters) unless otherwise noted Molded Plastic Quad Flat Package Order Number DP83843BVJE NC Package Number VJE80A 2. A critical component is any component of a life support ...