DP83257 National Semiconductor, DP83257 Datasheet
DP83257
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DP83257 Summary of contents
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... Supports single attach stations dual attach stations Y and concentrators with no external logic DP83256 for SAS DAS single path stations Y DP83257 for SAS DAS single dual path stations Y DP83256-AP for SAS DAS single path stations that re- Y quire the alternate PMD interface TL F 11708– ...
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... Recommended Operating Conditions Electrical Characteristics Electrical Characteristics 8 0 CONNECTION DIAGRAMS 8 1 DP83256VF Connection Diagram Pin Descriptions 8 2 DP83256VF-AP Connection Diagram Pin Descrip- tions 8 3 DP83257VF Connection Diagram Pin Descriptions 9 0 PACKAGE INFORMATION 9 1 Land Patterns 9 2 Mechanical Drawings 2 State Comparison ...
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... DP83256 56-AP for SAS DAS single path stations Y P83257 for SAS DAS single dual path stations Y In addition the DP83257 contains the additional PHY Da- ta request and PHY Data indicate ports required for con- centrators and dual attach dual path stations DP83266 MACSI ...
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... Device is an integrated circuit designed to inter- face directly with the serial bit streams of a Twisted Pair FDDI PMD The DP83222 is designed to be fully compatible with the National Semiconductor FDDI Chip Sets including twisted pair FDDI Transceivers such as the DP83223A Twisted Pair Transceiver (TWISTER) The DP83222 re- ...
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Architecture Description 2 1 BLOCK OVERVIEW The PLAYER device is comprised of six blocks Clock a Recovery Receiver Configuration Switch Transmitter Sta- tion Management (SMT) Support and Clock Generation Module as shown in Figure 2-1 Clock Recovery The ...
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... FDDI Physical Media Connection such as a fiber optic transceiver or a copper twisted pair transceiver 125 MHz full duplex serial connection The DP83256-AP and DP83257 PLAYER two PMD interfaces The Primary PMD Interface should be used for all PMD implementations that do not require an ...
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Functional Description The PLAYER device is comprised of six blocks Clock a Recovery Receiver Transmitter Configuration Switch Clock Generation and Station Management Support 3 1 CLOCK RECOVERY MODULE The Clock Recovery Module accepts a 125 Mbps NRZI data ...
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Functional Description Since the loop gain is held constant regardless of the in- coming signal edge density PLL characteristics such as jit- ter acquisition rate locking range etc are deterministic and show minimal spread under various operating environments ...
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Functional Description 3 2 RECEIVER BLOCK During normal operation the Receiver Block accepts serial data input at the rate of 125 Mbps from the Clock Recovery Module During the Internal Loopback mode of operation the Receiver Block accepts ...
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Functional Description Framing may be temporarily suspended (i e framing hold) in order to maintain data integrity Detecting JK The JK symbol pair can be used to detect the beginning of a frame during Active Line State (ALS) ...
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Functional Description Super Idle Line State The Line State Detector recognizes the incoming data the Super Idle Line State upon the reception of 8 consec- utive Idle symbol pairs nominally (plus 1 symbol pair) The ...
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Functional Description 3 3 TRANSMITTER BLOCK The Transmitter Block accepts 10-bit bytes consisting of 8 bits data 1 bit parity and 1 bit control information from the Configuration Switch The Transmitter Block performs the following operations Encodes the ...
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... Data bits represent Data or Control information When the control bit is 0 the Data field is interpreted as data and when the field is interpreted as control information according to the National Semiconductor control codes PARITY CHECKER The Parity Checker verifies that the parity bit in the Data ...
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Functional Description FIGURE 3-5 Repeat Filter State Diagram Note Inputs to the Repeat Filter state machine are shown above the transition lines while outputs from the state machine are shown below the transition lines Note Abbreviations used in ...
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Functional Description TABLE 3-3 Abbreviations used in the Repeat Filter State Diagram F IDLE Force Idle true when not in Active Transmit Mode W Represents the symbols TPARITY Parity error nn Data ...
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Functional Description LINE STATE GENERATOR The Line State Generator allows the transmission of the PHY Request data and can also generate and transmit Idle Master Halt or Quiet symbol pairs which can be used to implement the Connection ...
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... The Shift Register converts encoded parallel data to serial data The parallel data is clocked into the Shift Register by the Local Byte Clock (LBC1) and clocked out by the Trans- mit Bit Clock (TXC ) (externally available on the DP83257 ) g NRZ TO NRZI ENCODER The NRZ to NRZI Encoder converts the serial Non-Return- ...
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... Configuration Switch whereas the DP83256 and DP83256-AP have one set of PHY port interfaces The DP83257 uses the A Request and A Indicate paths as one PHY Port interface and the B Request and B Indi- cate paths as the other PHY Port interface (See Figure 3-8 ) ...
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... The DP83256 DP83256-AP and DP83257 can be used in a Single Attach Station The DP83256 and DP83256-AP can be connected to the MAC via its only PHY Port interface The DP83257 can be connected to the MAC via either one of its 2 PHY Port Interfaces See Figure 3-10 and Figure 3-11 ...
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... Functional Description FIGURE 3-12 Dual Attachment Station (DAS) Single MAC (DP83257) FIGURE 3-13 Dual Attachment Station (DAS) Single MAC (DP83256 56-AP) FIGURE 3-14 Dual Attachment Station (DAS) Dual MACs (Continued 11708 – 11708 – 11708 – 17 ...
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... The DP83256 DP83256-AP and DP83257 can be used to build a Single Attach concentrator See Application Note AN-675 Designing FDDI concentra- tors and Application Note AN-741 Differentiating FDDI con- centrators for further information ...
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Functional Description FIGURE 3-15 Single Attach Concentrator (SAC) Single MAC FIGURE 3-16 Dual Attach Concentrator (DAC) Single MAC FIGURE 3-17 Dual Attach Concentrator (DAC) Dual MACs (Continued 11708 – 11708 – 19 ...
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Functional Description 3 5 CLOCK GENERATION MODULE The Clock Generation Module is an integrated phase locked loop that generates all of the required clock signals for the PLAYER device and the rest of an FDDI system from a ...
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Functional Description The voltage on the Loop Filter is set by the current pulses generated by the Phase Comparator The voltage on the Loop Filter node controls the frequency of the 250 MHz VCO 250 MHZ VOLTAGE CONTROLLED ...
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Functional Description If the TCO Mask (TCOM) bit of the CMTCMR is set then whenever the CMTCR TCO bit becomes set the Receive Condition Register B’s Connection (RCRB CSE) bit will be set This allows an interrupt to ...
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Functional Description TABLE 3-5 Noise Event Description Noise Event ( (PB e Where Logical AND e Logical Logical NOT E ...
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Functional Description 3 7 PHY-MAC INTERFACE NATIONAL BYTE-WIDE CODE The PLAYER device outputs the National byte-wide code a from its PHY Port Indicate Output to the MAC device Each National byte-wide code may contain data or control codes ...
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Functional Description National Byte-Wide Code Example Incoming 5B Code Decoded 4B Code 98765 43210 C 3210 11111 11111 (II) 1 1010 11111 11111 (II) 1 1010 11111 11111 (II) 1 1010 11000 10001 (JK) 1 1101 –––- –––- ...
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... DP83257 PLAYER a or Shielded Twisted Pair (SDDI) PMD using the Primary devices contain PMD Interface Figure 3-21 shows how the DP83256-AP or DP83257 PLAYER device is connected to an Unshielded Twisted a Pair (UTP) PMD using the Alternate PMD Interface FIGURE 3-21 UTP PMD Connections ...
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Functional Description INTERFACE ACTIVATION The Primary PMD Interface is always enabled The Alternate PMD Interface is enabled by programming a PLAYER register bit To enable the interface write the APMDEN bit in the APMDREG ...
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... Configu- ration Switch Loopback mode ) See Figure 4-1 and Figure 4-2 device a FIGURE 4-1 Configuration Switch Loopback 7 0 BIP BIC l a device a FIGURE 4-2 Configuration Switch Loopback for DP83256 and DP 83256- 11708 – 23 for DP83257 TL F 11708 – 24 ...
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Modes of Operation (Continued) Short Internal Loopback The Short Internal Loopback mode can be used to test the functionality of the PLAYER device not including the a Clock Recovery function and to test the data paths be- tween ...
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Modes of Operation (Continued) Long Internal Loopback The Long Internal Loopback mode implements the longest loopback path that is completely within the PLAYER vice The Long Internal Loopback mode can be used to test the functionality of the ...
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Modes of Operation (Continued DEVICE RESET The revision B PLAYER device has five different levels of a device Reset Power Up Reset Hardware Reset Player Reset Reference Select Reset and Stop Mode The Re- sets can ...
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... CASCADE MODE The PLAYER device can operate in the Cascade (paral- a lel) mode (Figure 4-5) which is used in high bandwidth point-to-point data transfer applications This is a non-FDDI mode of operation This is only available on the DP83257 device Concepts In the Cascade mode multiple PLAYER devices are con- a ...
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Modes of Operation (Continued) FIGURE 4-6 Cascade Mode of Operation FIGURE 4-5 Parallel Transmission 11708 – 11708– 28 ...
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Registers The PLAYER device can be initialized configured and monitored using 64 8-bit registers These registers are accessible a through the Control Bus Interface The following tables summarize each register’s attributes Note RESERVED Registers may be read at ...
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Registers (Continued) TABLE 5-1 Register Summary (Continued) Register Register Address Symbol 1Dh RCCRB Receive Condition Comparison Register B 1Eh MODE2 Mode Register 2 1Fh CMTCCR CMT Condition Comparison Register 20h CMTCR CMT Condition Register 21h CMTMR CMT Condition ...
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Registers (Continued) Register Register Address Symbol D7 00h MR RNRZ TNRZ 01h CR BIE AIE 02h ICR UDI RCB 03h ICMR UDIM RCBM 04h CTSR RES PRDPE 05h IJTR IJT7 IJT6 06h ISRA RES RES 07h ISRB RES ...
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Registers (Continued) TABLE 5-2 Register Bit Summary (Continued) Register Register Address Symbol D7 23h RR23 RES RES 24h STTR STT7 STT6 25h STVR STV7 STV6 26h TDR TONT TOQLS 27h TTCR BIE AIE 28h RR28 RES RES 29h ...
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Registers (Continued) TABLE 5-3 Register Reset Value Summary Register Register Address Symbol 00h MR 01h CR 02h ICR 03h ICMR 04h CTSR 05h IJTR 06h ISRA 07h ISRB 08h CRSR 09h RCRA 0Ah RCRB 0Bh RCMRA 0Ch RCMRB ...
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Registers (Continued) TABLE 5-3 Register Reset Value Summary (Continued) Register Register Address Symbol 1Eh MODE2 1Fh CMTCCR 20h CMTCR 21h CMTMR 22h RR22 23h RR23 24h STTR 25h STVR 26h TDR 27h TTCR 28h RR28 29h RR29 2Ah ...
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... Disables synchronization of cascaded PLAYER 1 Enables the synchronization of cascaded PLAYER Refer to section 4 4 CASCADE MODE for more information Note Cascade Mode is only available on the DP83257 device The other devices do not have the required CS and CR pins Do not set this bit for any device but the DP83257 D4 ...
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... The CR is conditionally writable because the TTCR can be writing a new value into the register if this feature is enabled Note that the A Request and B Indicate port are offered only on the DP83257 and not in the DP83256 For further informa- tion refer to section 3 4 CONFIGURATION SWITCH ...
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Registers (Continued INTERRUPT CONDITION REGISTER (ICR) The Interrupt Condition Register records the occurrence of an internal error event the detection of Line State an unsuccessful write by the Control Bus Interface the expiration of an internal ...
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Registers (Continued) Bit Symbol D3 CWI CONDITIONAL WRITE INHIBIT Set to 1 when bits within mentioned registers do not match bits in the corresponding compare register This bit ensures that new (i e unread) data is not inadvertently ...
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Registers (Continued INTERRUPT CONDITION MASK REGISTER (ICMR) The Interrupt Condition Mask Register allows the user to dynamically select which events will generate an interrupt The Interrupt pin will be asserted ( INT to 1 ...
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Registers (Continued CURRENT TRANSMIT STATE REGISTER (CTSR) The Current Transmit State Register can program the Transmitter Block to internally generate and transmit Idle Master Halt Quiet or user programmable symbol pairs in addition to the normal ...
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Registers (Continued) Bit Symbol D3 D4 IC0 IC1 Injection Control over data from the Smoother Repeat Filter Encoder and Transmit Modes IC0 is the only bit of the register that is automatically cleared by the ...
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Registers (Continued INJECTION THRESHOLD REGISTER (IJTR) The Injection Threshold Register in conjunction with the Injection Control bits (IC (CTSR) set the frequency at which the contents of the Injection Symbol Register A (ISRA) and Injection Symbol ...
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Registers (Continued INJECTION SYMBOL REGISTER A (ISRA) The Injection Symbol Register A along with Injection Symbol Register B contains the programmable value (already in 5B code) that can be inserted to replace the data symbol pairs ...
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Registers (Continued INJECTION SYMBOL REGISTER B (ISRB) The Injection Symbol Register B along with Injection Symbol Register A contains the programmable value (already in 5B code) that will replace the data symbol pairs In One Shot ...
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Registers (Continued CURRENT RECEIVE STATE REGISTER (CRSR) The Current Receive State Register represents the current line state being detected by the Receiver Block When the Receiver Block recognizes a new Line State the bits corresponding to ...
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Registers (Continued RECEIVE CONDITION REGISTER A (RCRA) The Receive Condition Register A maintains a historical record of the Line States recognized by the Receiver Block When a new Line State is entered the bit corresponding to ...
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... When a synchronization error occurs the Cascade Synchronization Error bit is set synchronization error occurs if the Cascade Start signal (CS) is not asserted within approximately Cascade Ready (CR) release Note Cascade mode and the CMT features can not be used at the same time Note Cascade mode is only supported on the DP83257 device D5 EBOU ...
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Registers (Continued RECEIVE CONDITION MASK REGISTER A (RCMRA) The Receive Condition Mask Register A allows the user to dynamically select which events will generate an interrupt The Receive Condition A bit (RCA) of the Interrupt Condition ...
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Registers (Continued RECEIVE CONDITION MASK REGISTER B (RCMRB) The Receive Condition Mask Register B allows the user to dynamically select which events will generate an interrupt The Receive Condition B bit (RCB) of the Interrupt Condition ...
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Registers (Continued NOISE THRESHOLD REGISTER (NTR) The Noise Threshold Register contains the start value for the Noise Timer This threshold register is used in conjunction with the Noise Prescale Threshold register for setting the maximum allowable ...
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Registers (Continued NOISE PRESCALE THRESHOLD REGISTER (NPTR) The Noise Prescale Threshold Register contains the start value for the Noise Prescale Timer This threshold register is used in conjunction with the Noise Threshold register for setting the ...
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Registers (Continued CURRENT NOISE COUNT REGISTER (CNCR) The Current Noise Count Register takes a snap-shot of the Noise Timer during every Control Bus Interface read cycle of this register During a Control Bus Interface write cycle ...
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Registers (Continued CURRENT NOISE PRESCALE COUNT REGISTER (CNPCR) The Current Noise Prescale Count Register takes a snap-shot of the Noise Prescale Timer during every Control Bus Interface read cycle of this register During a Control Bus ...
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Registers (Continued STATE THRESHOLD REGISTER (STR) The State Threshold Register contains the start value for the State Timer This timer is used in conjunction with the State Prescale Timer to count the Line State duration The ...
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Registers (Continued STATE PRESCALE THRESHOLD REGISTER (SPTR) The State Prescale Threshold Register contains the start value for the State Prescale Timer The State Prescale Timer is a down counter It is used in conjunction with the ...
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Registers (Continued CURRENT STATE COUNT REGISTER (CSCR) The Current State Count Register takes a snap-shot of the State Counter during every Control Bus Interface read cycle of this register During a Control Bus Interface write cycle ...
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Registers (Continued CURRENT STATE PRESCALE COUNT REGISTER (CSPCR) The Current State Prescale Count Register takes a snap-shot of the State Prescale Counter during every Control Bus Interface read cycle of this register During a Control Bus ...
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Registers (Continued LINK ERROR THRESHOLD REGISTER (LETR) The Link Error Threshold Register contains the start value for the Link Error Monitor Counter 8-bit down-counter which decrements if link errors are detected When the ...
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Registers (Continued CURRENT LINK ERROR COUNT REGISTER (CLECR) The Current Link Error Count Register takes a snap-shot of the Link Error Monitor Counter during every Control Bus Interface read cycle of this register During a Control ...
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... D6 EB2 ENABLE BIT2 The Enable Bit 2 allows control of external logic through the Control Bus Interface The User Definable Enable Pin 2 (EP2) is asserted deasserted by this bit Note SB2 and EB2 are only effective for the DP83257 0 EP2 is deasserted (i e EP2 1 EP2 is asserted (i e EP2 ...
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Registers (Continued DEVICE ID REGISTER (IDR) The Device ID Register contains the binary equivalent of the revision number for this device It can be used to ensure proper software and hardware versions are matched During a ...
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Registers (Continued CURRENT INJECTION COUNT REGISTER (CIJCR) The Current Injection Count Register takes a snap-shot of the Injection Counter during every Control Bus Interface read cycle of this register During a Control Bus Interface write cycle ...
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Registers (Continued INTERRUPT CONDITION COMPARISON REGISTER (ICCR) The Interrupt Condition Comparison Register ensures that the Control Bus must first read a bit modified by the PLAYER device before it can be written to by the Control ...
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Registers (Continued CURRENT TRANSMIT STATE COMPARISON REGISTER (CTSCR) The Current Transmit State Comparison Register ensures that the Control Bus must first read a bit modified by the PLAYER device before it can be written to by ...
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Registers (Continued RECEIVE CONDITION COMPARISON REGISTER A (RCCRA) The Receive Condition Comparison Register A ensures that the Control Bus must first read a bit modified by the PLAYER device before it can be written to by ...
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Registers (Continued RECEIVE CONDITION COMPARISION REGISTER B (RCCRB) The Receive Condition Comparison Register B ensures that the Control Bus must first read a bit modified by the PLAYER device before it can be written to by ...
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Registers (Continued MODE REGISTER 2 (MODE2) The Mode Register 2 (MODE2) is used to configure the PLAYER The register is used to software reset the chip setup data parity and enable scrubbing functions Note This register ...
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Registers (Continued CMT CONDITION COMPARISON REGISTER (CMTCCR) The CMT Condition Comparison Register (CMTCR) ensures that the Control Bus must first read a bit modified by the PLAYER device before it can be written to by the ...
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Registers (Continued CMT CONDITION REGISTER (CMTCR) The CMT Condition Register maintains a history of all CMT events and actions performed The corresponding CMT Condition Mask Register (CMTCMR) can be used to generate an interrupt When the ...
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Registers (Continued CMT CONDITION MASK REGISTER (CMTCMR) This is the mask register for the CMT Condition Register (CMTCR) When the bits in both the CMTCMR and CMTCR are set the Receive Condition Register B’s Connection Service ...
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Registers (Continued RESERVED REGISTERS 22H–23H (RR22H–RR23H) This register is reserved for future use DO NOT ACCESS THIS REGISTER ACCESS RULES ADDRESS READ 22h –23h Always DO NOT WRITE WRITE 79 ...
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Registers (Continued SCRUB TIMER THRESHOLD REGISTER (STTR) This is the threshold value of the internal scrub timer It has a resolution and a maximum value When the scrub ...
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Registers (Continued SCRUB TIMER VALUE REGISTER (STVR) This is a snap-shot of the current value of the upper 8 bits of the scrub timer During a Control Bus Interface write cycle the Control Bus Write Command ...
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Registers (Continued TRIGGER DEFINITION REGISTER (TDR) This register determines which events cause a trigger transition and which transmit mode is entered when a trigger transition is detected The trigger transmit modes are the same as those ...
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Registers (Continued TRIGGER TRANSITION CONFIGURATION REGISTER (TTCR) The Trigger Transition Configuration Register holds the configuration switch setting to be loaded into the Configuration Register (CR) when a trigger transition takes place When scrubbing is enabled scrubbing ...
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Registers (Continued RESERVED REGISTERS 28H-3AH (RR28H-RR3AH) These registers are reserved for future use DO NOT ACCESS THESE REGISTERS ACCESS RULES ADDRESS READ 28h –3Ah Always DO NOT WRITE WRITE 84 ...
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... TXCE TRANSMIT CLOCK ENABLE When bit is set to 1 125 MHz ECL TXC outputs are enabled When this bit is reset to 0 TXC outputs are disabled TXC outputs are disabled on reset Note TXC clocks are only available on the 160-pin DP83257 PLAYER D4 RES RESERVED BITS DO NOT CHANGE THE VALUE OF THESE BITS Changes to reserved register bits could ...
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... In some alternate PMD implementations it may also be necessary to use the 125 MHz Transmit Clock signals (TXC) The TXC outputs must be separately enabled by the TXCE bit in the CGMREG register Note The Alternate PMD Interface pins are only available on the 100-pin DP83256-AP and 160-pin DP83257 PLAYER Alternate PMD Interface is disabled on reset D4 – ...
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Registers (Continued GAIN REGISTER (GAINREG) The Gain Register contains the settings for the CGM’s on-chip programmable loop filter For optimal jitter performance on the revision A and B PLAYER device’s Filter Position 4 should be used ...
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Registers (Continued RESERVED REGISTERS 3EH-3FH (RR3EH-RR3FH) These registers are reserved for future use DO NOT ACCESS THESE REGISTERS ACCESS RULES ADDRESS READ 3Eh –3Fh Always DO NOT WRITE WRITE 88 ...
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Signal Descriptions 6 1 DP83256VF PIN DESCRIPTIONS The pin descriptions for the DP83256VF are divided into 5 functional interfaces PMD Interface PHY Port Interface Control Bus Interface Clock Interface and Miscellaneous Interface For a Pinout Summary list refer ...
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Signal Descriptions (Continued) PHY PORT INTERFACE The PHY Port Interface consists signals used to connect the PLAYER sublayer or other PLAYER device The DP83256 Device has two PHY Port Interfaces The A Indicate path from ...
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Signal Descriptions (Continued) CONTROL BUS INTERFACE The Control Bus Interface consists signals used to connect the PLAYER The Control Bus is an asynchronous interface between the PLAYER controller It provides access to 64 8-bit internal ...
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Signal Descriptions (Continued) CLOCK INTERFACE The Clock Interface consists MHz and 25 MHz clocks supplied by the PLAYER feedback inputs Symbol Pin I O LBC1 4 O Local Byte Clock TTL compatible 12 5 MHz ...
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Signal Descriptions (Continued) MISCELLANEOUS INTERFACE The Miscellaneous Interface consist of a reset signal user definable sense signals and user definable enable signals Symbol Pin RST 71 I Reset An active low TTL input signal which ...
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Signal Descriptions (Continued) POWER AND GROUND All power pins should be connected to a single connected to a common 0V ground supply Bypassing and filtering requirements are given in a separate User Information Document Symbol Pin I O ...
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Signal Descriptions (Continued DP83256VF-AP SIGNAL DESCRIPTIONS The pin descriptions for the DP83256VF-AP are divided into five functional interfaces PMD Interface PHY Port Interface Control Bus Interface Clock Interface and Miscellaneous Interface For a Pinout Summary List ...
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Signal Descriptions (Continued) Alternate PMD Interface Symbol Pin I O PMID 42 I PMD Indicate Data Differential 100k ECL 125 Mbps serial data input signals from the PMD a Receiver into the Clock Recovery Module (CRM) of the ...
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Signal Descriptions (Continued) PHY PORT INTERFACE The PHY Port Interface consists signals used to connect the PLAYER sublayer or other PLAYER device The DP83256 Device has two PHY Port Interfaces The A Indicate path from ...
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Signal Descriptions (Continued) CONTROL BUS INTERFACE The Control Bus Interface consists signals used to connect the PLAYER The Control Bus is an asynchronous interface between the PLAYER controller It provides access to 64 8-bit internal ...
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Signal Descriptions (Continued) CLOCK INTERFACE The Clock Interface consists MHz and 25 MHz clocks supplied by the PLAYER feedback inputs Symbol Pin I O LBC1 4 O Local Byte Clock TTL compatible 12 5 MHz ...
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Signal Descriptions (Continued) MISCELLANEOUS INTERFACE The Miscellaneous Interface consist of a reset signal and user definable enable signals Symbol Pin RST 71 I Reset An active low TTL input signal which clears all registers The ...
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Signal Descriptions (Continued) POWER AND GROUND All power pins should be connected to a single connected to a common 0V ground supply Bypassing and filtering requirements are given in a separate User Information Document Symbol Pin I O ...
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... The pin descriptions for the DP83257VF are divided into five functional interfaces PMD Interface PHY Port Interface Control Bus Interface Clock Interface and Miscellaneous Interface For a Pinout Summary List refer to Table 8-3 and Figure 8-3 DP83257VF 160-Pin JEDEC Metric PQFP Pinout PMD INTERFACE ...
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Signal Descriptions (Continued) Alternate PMD Interface Symbol Pin I O PMID 62 I PMD Indicate Data Differential 100k ECL 125 Mbps serial data input signals from the PMD a Receiver into the Clock Recovery Module (CRM) of the ...
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... The PHY Port Interface consists signals used to connect the PLAYER sublayer or other PLAYER device The DP83257 Device has two PHY Port Interfaces The A Request and A Indicate paths a from one PHY Port Interface and the B Request and B Indicate paths from the second PHY Port Interface Each path ...
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Signal Descriptions (Continued) Symbol Pin I O BRD7 111 I PHY Port B Request Data TTL input signals representing the first 4-bit data control symbol BRD6 109 BRD7 is the most significant bit and BRD4 is the least ...
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Signal Descriptions (Continued) CONTROL BUS INTERFACE The Control Bus Interface consists signals used to connect the PLAYER The Control Bus is an asynchronous interface between the PLAYER controller It provides access to 64 8-bit internal ...
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Signal Descriptions (Continued) CLOCK INTERFACE The Clock Interface consists MHz and 25 MHz clocks supplied by the PLAYER feedback inputs Symbol Pin I O LBC1 4 O Local Byte Clock TTL compatible 12 5 MHz ...
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Signal Descriptions (Continued) MISCELLANEOUS INTERFACE The Miscellaneous Interface consist of a reset signal user definable sense signals and user definable enable signals Symbol Pin RST 116 I Reset An active low TTL input signal which ...
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Signal Descriptions (Continued) POWER AND GROUND All power pins should be connected to a single connected to a common 0V ground supply Bypassing and filtering requirements are given in a separate User Information Document Symbol Pin I O ...
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Electrical Characteristics 7 1 ABSOLUTE MAXIMUM RATINGS Symbol Parameter V Supply Voltage CC DC Input Voltage IN DC Output Voltage OUT V ESD to other Maximum Voltage Differential Storage Temperature ECL Signal Output Current ESD ...
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Electrical Characteristics DC Electrical Characteristics for All TTL-Compatible Non-TRI-STATE Outputs The following signals are covered Clock 16 32 (CLK16) Enable Pins (EP) and PMD Transmitter Enable (TXE) Symbol Parameter V Output High Voltage OH V Output Low Voltage ...
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Electrical Characteristics DC Electrical Characteristics for All FDDI Clock Outputs The following signals are covered Local Byte Clocks (LBC1– LBC5) and Local Symbol Clock (LSC) These outputs are designed to drive capacitive loads from ...
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Electrical Characteristics DC Electrical Characteristics for All 100K ECL Compatible Inputs The following signals are covered PMD Indicate Data (PMID) Receive Clock In (RXC IN) Receive Data In (RXD IN) and Signal Detect (SD) Symbol Parameter V Input ...
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Electrical Characteristics ELECTRICAL CHARACTERISTICS The AC Electrical characteristics are specified over the Recommended Operating Conditions unless otherwise specified AC Characteristics for the Control Bus Interface The following signals are covered Control Bus Interface (R E ...
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Electrical Characteristics FIGURE 7-1 Asynchronous Control Bus Write Cycle Timing FIGURE 7-2 Asynchronous Control Bus Read Cycle Timing (Continued) 115 TL F 11708 – 11708 – 30 ...
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Electrical Characteristics FIGURE 7-3 Control Bus Synchronous Writes FIGURE 7-4 Control Bus Synchronous Reads FIGURE 7-5 Control Bus Interrupt Timing (Continued 11708 – 50 116 TL F 11708 – 11708 – 32 ...
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Electrical Characteristics AC Characteristics for the Clock Interface Signals (Timing and Relationships) Symbol Parameter T LBC1–LBC2 Timing Phase1 T LBC1–LBC3 Timing Phase2 T LBC1–LBC4 Timing Phase3 T LBC1–LBC5 Timing Phase4 T LBC1–LBC2 Timing Phase1 T LBC1–LBC3 Timing Phase2 ...
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Electrical Characteristics FIGURE 7-7 Typical Clock Signal Relationships Based on Phase Select (PH SEL) Setting (Continued) 118 TL F 11708 – 51 ...
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Electrical Characteristics AC Characteristics for the Clock Interface Signals (Periods and Pulse Widths) Symbol Parameter T2 LBC Period T9 LBC Pulse Width High T10 LBC Pulse Width Low T25 LSC Pulse Width High T26 LSC Pulse Width Low ...
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Electrical Characteristics AC Characteristics for the PMD Interface The following signals are covered PMD Indicate Data (PMID) Signal Detect (SD) and PMD Request Data (PMRD) Symbol Parameter T36 PMID to PMRD Latency g g T37 SD Minimum Pulse ...
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... The following output signals are covered PMD Request Data (PMRD) Transmit Clock (TXC) Recovered Data Out (RXD OUT) Recovered Clock Out (RXC OUT) Note The Alternate PMD Interface is only available on the 160 pin DP83257 PLAYER enabled by the CGMREG TXCE bit The rest of the Alternate PMD Interface is enabled by the APMDREG APMDEN bit ...
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Electrical Characteristics FIGURE 7-12 Alternate PMD Timing Diagrams (Continued) 122 TL F 11708 – 53 ...
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... The following input signals are covered PMD Indicate Data (PMID) Receive Data In (RXD IN) Receive Clock In (RXC IN) Note The Alternate PMD Interface is only available on the 160 pin DP83257 PLAYER enabled by the CGMREG TXCE bit The rest of the Alternate PMD Interface is enabled by the APMDREG APMDEN bit ...
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... The following output signals are covered PMD Request Data (PMRD) Transmit Clock (TXC) Recovered Data Out (RXD OUT) Recovered Clock Out (RXC OUT) Note The Alternate PMD Interface is only available on the 160 pin DP83257 PLAYER enabled by the CGMREG TXCE bit The rest of the Alternate PMD Interface is enabled by the APMDREG APMDEN bit ...
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Electrical Characteristics AC Characteristics for User Definable Pins The following signals are covered Sense Pins (SP) For Enable Pins (EP) timing see AC Characteristics for the Control Bus Interface Symbol Parameter T59 SP Minimum Pulse Width FIGURE 7-14 ...
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Electrical Characteristics AC TEST CIRCUITS Note S is closed for T and T 1 PZL PLZ S is closed for T and T 2 PZH PHZ S and S are open otherwise 1 2 FIGURE 7-16 Switching Test ...
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Electrical Characteristics TEST WAVEFORMS FIGURE 7-20 ECL Output Test Waveform Note All CMOS Inputs and outputs are TTL compatible FIGURE 7-21 TTL Output Test Waveform FIGURE 7-22 TRI-STATE Output Test Waveform (Continued 11708– ...
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Connection Diagrams 8 1 DP83256VF CONNECTION DIAGRAM For a Pinout Summary List refer to Table 8-1 FIGURE 8-1 DP83256VF 100-Pin JEDEC Metric PQFP Pinout 128 TL F 11708 – 44 ...
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Connection Diagrams (Continued) TABLE 8-1 DP83256 100-Pin PQFP Pinout Summary Pin No Signal Name 1 Local Byte Clock 4 2 Local Byte Clock 3 3 Local Byte Clock 2 4 Local Byte Clock 1 5 Clock 16 32 ...
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Connection Diagrams (Continued) TABLE 8-1 DP83256 100-Pin PQFP Pinout Summary (Continued) Pin No Signal Name 39 PMD Indicate Data 40 Sense Pin 0 41 Enable Pin 0 42 Sense Pin 1 43 Enable Pin 1 44 ECL Power ...
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Connection Diagrams (Continued) TABLE 8-1 DP83256 100-Pin PQFP Pinout Summary (Continued) Pin No Signal Name 77 Control Bus Address Logic Ground Logic Power 80 Control Bus Address 81 Control Bus Address 82 ...
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Connection Diagrams (Continued DP83256VF-AP CONNECTION DIAGRAM For a Pinout Summary List refer to Table 8-2 FIGURE 8-2 DP83256VF-AP 100-Pin JEDEC Metric PQFP Pinout 132 TL F 11708 – 58 ...
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Connection Diagrams (Continued) TABLE 8-2 DP83256VF-AP 100-Pin PQFP Pinout Summary Pin No Signal Name 1 Local Byte Clock 4 2 Local Byte Clock 3 3 Local Byte Clock 2 4 Local Byte Clock 1 5 Clock 16 32 ...
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Connection Diagrams (Continued) TABLE 8-2 DP83256VF-AP 100-Pin PQFP Pinout Summary (Continued) Pin No Signal Name 39 Signal Detect b 40 Signal Detect a 41 PMD Indicate Data b 42 PMD Indicate Date a 43 Enable Pin 0 44 ...
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Connection Diagrams (Continued) TABLE 8-2 DP83256VF-AP 100-Pin PQFP Pinout Summary (Continued) Pin No Signal Name 77 Control Bus Address Logic Ground Logic Power 80 Control Bus Address 81 Control Bus Address 82 ...
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... Connection Diagrams (Continued DP83257VF CONNECTION DIAGRAM For a Pinout Summary List refer to Table 8-3 FIGURE 8-3 DP83257VF 160-Pin JEDEC Metric PQFP Pinout 136 TL F 11708 – 45 ...
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... Connection Diagrams (Continued) TABLE 8-3 DP83257 160-Pin PQFP Pinout Summary Pin No Signal Name 1 Local Byte Clock 4 2 Local Byte Clock 3 3 Local Byte Clock 2 4 Local Byte Clock 1 5 Clock PHY Port A Indicate Parity 7 PHY Port A Request Parity 8 PHY Port A Indicate Control ...
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... Connection Diagrams (Continued) TABLE 8-3 DP83257 160-Pin PQFP Pinout Summary (Continued) Pin No Signal Name 39 No Connect 40 No Connect 41 No Connect 42 No Connect 43 No Connect 44 No Connect 45 Crystal Output 46 Crystal Input 47 ESD Power 48 ESD Ground 49 Loop Filter 50 Transmit Clock b 51 Transmit Clock ...
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... Connection Diagrams (Continued) TABLE 8-3 DP83257 160-Pin PQFP Pinout Summary (Continued) Pin No Signal Name 77 Receive Data Receive Data Connect 80 No Connect 81 No Connect 82 Receive Data Out b 83 Receive Data Out a 84 Reserved 0 85 Reserved 0 86 Reserved Connect 88 ECL Ground 89 ECL Power ...
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... Connection Diagrams (Continued) TABLE 8-3 DP83257 160-Pin PQFP Pinout Summary (Continued) Pin No Signal Name 115 PHY Port B Request Parity 116 E Device Reset 117 Read E Write 118 Chip Enable 119 E Interrupt 120 E Acknowledge 121 No Connect 122 No Connect 123 No Connect 124 No Connect ...
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... Connection Diagrams (Continued) TABLE 8-3 DP83257 160-Pin PQFP Pinout Summary (Continued) Pin No Signal Name 152 No Connect 153 No Connect 154 No Connect 155 No Connect 156 No Connect 157 I O Ground 158 I O Power 159 Local Symbol Clock 160 Local Byte Clock5 Symbol GND IO ...
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... TABLE 9-1 Layout Land Pattern Dimensions Device DP83256VF and DP83256VF-AP 14mm x 14mm x 2 0mm 100-lead JEDEC FPQFP DP83257VF 28mm x 28mm x 3 42mm 160-lead JEDEC MQFP 9 2 MECHANICAL DRAWINGS The following two pages contain the mechanical drawings for each of the available PLAYER ...
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Physical Dimensions millimeters Order Number DP83256VF and DP83256VF-AP Plastic Quad Flatpak (VJU) NS Package Number VJU100A 143 ...
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... National does not assume any responsibility for use of any circuitry described no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications Plastic Quad Flatpak (V) Order Number DP83257VF NS Package Number VUL160A 2 A critical component is any component of a life ...