DP83916 National Semiconductor, DP83916 Datasheet
DP83916
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DP83916 Summary of contents
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... TM DP83916 SONIC -16 Systems-Oriented Network Interface Controller General Description The SONIC TM -16 (Systems-Oriented Network Interface Controller second-generation Ethernet Controller de- signed to meet the demands of today’s high-speed 16-bit systems Its system interface operates with a high speed DMA that typically consumes less than 8% of the bus band- ...
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FUNCTIONAL DESCRIPTION 1 1 IEEE 802 3 ENDEC Unit ENDEC Operation Selecting an External ENDEC 1 2 MAC Unit MAC Receive Section MAC Transmit Section 1 ...
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Functional Description The SONIC-16 (Figure 1-1 ) consists of an encoder decoder (ENDEC) unit media access control (MAC) unit separate receive and transmit FIFOs a system buffer management engine and a user programmable system bus interface unit on ...
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Functional Description (Continued) 4 ...
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Functional Description network The ENDEC section detects this when its collision receiver detects a 10 MHz signal on the differential collision input pair The ENDEC also provides both the receive and transmit clocks to the MAC unit The ...
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Functional Description During transmission of a packet from the SONIC-16 the external transceiver will always loop the packet back to the SONIC-16 The SONIC-16 will use this to monitor the packet being transmitted The CRC ...
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Functional Description Serializer After data has been written into the 32-byte transmit FIFO the serializer reads byte wide data from the FIFO and sends a NRZ data stream to the Manchester en- coder The rate at which data ...
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Functional Description 1 4 FIFO AND CONTROL LOGIC The SONIC-16 incorporates two independent 32-byte FIFOs for transferring data to from the system interface and from to the network The FIFOs providing temporary stor- age of data free the ...
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Functional Description 1 5 STATUS AND CONFIGURATION REGISTERS The SONIC-16 contains a set of status control registers for conveying status and control information to from the host system The SONIC-16 uses these registers for loading commands generated from ...
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Functional Description 4 Program the Receive Control register with the desired re- ceive filter and the loopback mode (LB1 LB0) 5 Issue the transmit command (TXP) and enable the receiv- er (RXEN) in the Command register The SONIC-16 ...
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Functional Description TABLE 1-1 Network Management Statistics Statistic Frames Transmitted OK Single Collision Frames Multiple Collision Frames Collision Frames Frames with Deferred Transmissions Late Collisions Excessive Collisions Excessive Deferral Internal MAC Transmit Error Frames Received OK Multicast Frames ...
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Transmit Receive IEEE 802 3 Frame Format ets from reaching a node There are three types of address formats supported by the SONIC-16 Physical Multicast and Broadcast Physical Address The physical address is a unique ad- dress that ...
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Buffer Management 3 1 BUFFER MANAGEMENT OVERVIEW The SONIC-16’s buffer management scheme is based on separate buffers and descriptors ( Figures 3-2 and 3-11 ) Packets that are received or transmitted are placed in buff- ers called the ...
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Buffer Management (Continued) TRANSMIT AND RECEIVE AREAS RRA Receive Resource Area RDA Receive Descriptor Area RBA Receive Buffer Area TDA Transmit Descriptor Area TBA Transmit Buffer Area BUFFER MANAGEMENT REGISTERS RSA Resource Start Area Register REA Resource End ...
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Buffer Management (Continued DESCRIPTOR DATA ALIGNMENT All fields used by descriptors (RXpkt xxx RXrsrc xxx and TXpkt xxx) are word quantities (16-bit) and must be aligned to word boundaries (A0 0) The Receive Buffer Area e ...
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Buffer Management (Continued Receive Buffer Area (RBA) The SONIC-16 stores the actual data of a received packet in the RBA The RBAs are designated by the resource de- scriptors in the RRA as described RXrsrc ...
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Buffer Management (Continued Receive Descriptor Area (RDA) After the SONIC-16 buffers a packet to memory it writes 5 words of status and control information into the RDA reads the link field to the next receive ...
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Buffer Management (Continued) All RRA registers are concatenated with the URRA register for generating the full 23-bit address The resource descriptors that the system writes to the RRA consists of four fields (1) RXrsrc buff ptr0 RXrsrc buff ...
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Buffer Management (Continued) An example would be EOBC 759 words (1518 bytes) and e the buffer size set to 760 words (1520 bytes) The buffer can be any size but as long as the EOBC is 1 word ...
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Buffer Management (Continued) when its receive resources have been exhausted The sys- tem should respond by replenishing the resources that have been exhausted These overflow conditions (Descriptor Re- sources Exhausted Buffer Resources Exhausted and RBA Limit Exceeded) are ...
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Buffer Management (Continued 11722– 19 FIGURE 3-12 Transmit Descriptor Area Transmit Configuration The TXpkt config field allows the SONIC- pro- grammed into one of the transmit modes before each trans- ...
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Buffer Management (Continued) TXpkt config to TXpkt frag size (6 accesses) For the next fragment if any it reads the next 3 fields from TXpkt frag ptr0 to TXpkt frag size (3 accesses) At the end of trans- ...
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SONIC-16 Registers (Continued) the SONIC- software reset The CDA resides in the same 64k byte block of memory as the Receive Resource Area (RRA) and contains descriptors for loading the CAM registers These descriptors are contiguous ...
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SONIC-16 Registers (Continued Command Register 1 Data Configuration Register 2 Receive Control Register Status and Control Registers 3 Transmit Control Register 4 Interrupt Mask Register 5 Interrupt Status Register 3F Data Configuration ...
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SONIC-16 Registers (Continued STATUS CONTROL REGISTERS This set of registers is used to convey status control infor- mation to from the host system and to control the operation of the SONIC-16 These registers are used for ...
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SONIC-16 Registers (Continued) RA5–RA0 Access WATCHDOG COUNTERS SILICON REVISION 28 R Note 1 These registers can only be read when the SONIC- reset mode (RST bit in the CR is ...
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SONIC-16 Registers (Continued REGISTER DESCRIPTION Command Register ( 0h This register (Figure 4 used for issuing commands to the SONIC-16 These commands are issued by setting ...
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SONIC-16 Registers (Continued REGISTER DESCRIPTION Command Register (Continued Bit 3 RXEN RECEIVER ENABLE Setting this bit enables the receive buffer management engine to begin buffering data ...
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SONIC-16 Registers (Continued Data Configuration Register ( 1h This register (Figure 4-5) establishes the bus cycle options for reading writing data to from 16- or 32-bit memory systems During a ...
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SONIC-16 Registers (Continued Data Configuration Register (Continued Bit 10 SBUS SYNCHRONOUS BUS MODE The SBUS bit is used to select the mode of system bus operation when SONIC-16 ...
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SONIC-16 Registers (Continued Receive Control Register ( 2h This register is used to filter incoming packets and provide status information of accepted packets (Figure 4-6) Setting any of bits 15 ...
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SONIC-16 Registers (Continued Receive Control Register (Continued Bit 10 9 LB1 LB0 LOOPBACK CONTROL These encoded bits control loopback operations for MAC loopback ENDEC loopback and Transceiver lookback ...
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SONIC-16 Registers (Continued Transmit Control Register ( 3h This register is used to program the SONIC-16’s transmit actions and provide status information after a packet has been transmitted (Figure 4-7) ...
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SONIC-16 Registers (Continued Transmit Control Register (Continued Bit 9 DEF DEFERRED TRANSMISSION Indicates that the SONIC-16 has deferred its transmission during the first attempt If subsequent collisions occur ...
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SONIC-16 Registers (Continued Interrupt Mask Register ( 4h This register masks the interrupts that can be generated from the ISR (Figure 4–8) Writing a ‘‘1’’ to the bit enables the ...
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SONIC-16 Registers (Continued Interrupt Mask Register (Continued Bit 7 TCEN GENERAL PURPOSE TIMER COMPLETE enable 0 disable 1 enables interrupts when the general purpose timer has rolled over ...
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SONIC-16 Registers (Continued Interrupt Status Register ( 5h This register (Figure 4-9) indicates the source of an interrupt when the INT pin goes active Enabling the corresponding bits in the ...
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SONIC-16 Registers (Continued Interrupt Status Register (Continued Bit 8 TXER TRANSMIT ERROR Indicates that a packet has been transmitted with at least one of the following errors Byte ...
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SONIC-16 Registers (Continued Data Configuration Register 2 ( 3Fh This register (Figure 4-10) is for enabling the extended bus interface options A hardware reset will set all bits in this ...
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SONIC-16 Registers (Continued Transmit Registers The transmit registers described in this section are part of the User Register set The UTDA and CTDA must be initial- ized prior to issuing the transmit command (setting the ...
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SONIC-16 Registers (Continued CAM Registers The CAM registers described in this section are part of the User Register set They are used to program the Content Addressable Memory (CAM) entries that provide address filtering of ...
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SONIC-16 Registers (Continued General Purpose Timer The SONIC-16 contains a 32-bit general-purpose watchdog timer for timing user-definable events This timer is ac- cessed by the user through two 16-bit read write registers (WT1 and WT0) ...
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Bus Interface (Continued) FIGURE 5-1 Connection Diagram (BMODE 11722 – 23 ...
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Bus Interface (Continued) FIGURE 5-2 Connection Diagram (BMODE 11722 – 24 ...
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Bus Interface (Continued PIN DESCRIPTION I input e O output and e Z TRI-STATE Inputs are TTL compatible e ECL ECL-like drivers for interfacing to the AUI interface e TP Totem pole like drivers These drivers ...
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Bus Interface (Continued) Driver Symbol Direction Type NETWORK INTERFACE PINS (Continued) RXDo TP O RXDi I EXUSR0 TRI O Z RXCo TP O RXCi I EXUSR1 TRI O Z TXD TP O EXUSR3 TRI O Z TXE TP ...
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Bus Interface (Continued) Driver Symbol Direction Type NETWORK INTERFACE PINS (Continued) LBK TP O EXUSR2 TRI O Z PCOMP TRI O Z SEL I PREJ BUS INTERFACE PINS BMODE I ...
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Bus Interface (Continued) Driver Symbol Direction Type BUS INTERFACE PINS (Continued) A31 –A1 TRI O Z RA5 –RA0 I AS TRI ADS TRI O Z MRW TRI O Z MWR TRI O Z INT OC ...
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Bus Interface (Continued) Driver Symbol Direction Type BUS INTERFACE PINS (Continued SAS I SDS I SRW I SWR I DS TRI O Z DSACK0 TRI RDYi I DSACK1 TRI RDYo ...
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Bus Interface (Continued) Driver Symbol Direction Type SHARED-MEMORY ACCESS PINS MREQ I SMACK TP O USER DEFINABLE PINS USR0 1 TRI POWER AND GROUND PINS VCC1 –5 TXVCC RXVCC PLLVCC VCCL GND1–6 TXGND ANGND GNDL ...
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Bus Interface (Continued SYSTEM CONFIGURATION Any device that meets the SONIC-16 interface protocol and electrical requirements (timing threshold and loading) can be interfaced to SONIC-16 Since two bus protocols are pro- vided via the BMODE pin ...
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Bus Interface (Continued) FIGURE 5-4 SONIC-16 to Motorola 68030 20 Interface Example 11722 – 26 ...
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Bus Interface (Continued Acquiring The Bus The SONIC-16 requests the bus when 1) its FIFO threshold has been reached or 2) when the descriptor areas in memo RRA RDA CDA and TDA) ...
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Bus Interface (Continued) FIGURE 5-6 Bus Request Timing BMODE Block Transfers The SONIC-16 performs block operations during all bus ac- tions thereby providing efficient transfers to memory The block cycle consists of three parts The ...
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Bus Interface (Continued Bus Status Transitions When the SONIC-16 acquires the bus it only transfers data to from a single area in memory (i e TDA TBA RDA RBA RRA or CDA) Thus the ...
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Bus Interface (Continued Master Mode Bus Cycles In order to add additional compatibility with different bus architectures there are two other modes that affect the op- eration of the bus These modes are called the ...
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Bus Interface (Continued Memory Cycle for BMODE 1 Synchronous e Mode On the rising edge of T1 the SONIC-16 asserts ECS to indicate that the memory cycle is starting The address (A31 –A1) bus ...
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Bus Interface (Continued Memory Cycle for BMODE 1 e Asynchronous Mode On the rising edge of T1 the SONIC-16 asserts ECS to indicate that the memory cycle is starting The address (A23 –A1) bus ...
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Bus Interface (Continued) bus clocks after DSACK0 1 were sampled or 1 cycle after STERM was sampled T2 states will be repeated until DSACK0 1 or STERM are sampled properly in a low state (see note below) During ...
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Bus Interface (Continued Memory Cycle for BMODE 0 Synchronous e Mode On the rising edge of T1 the SONIC-16 asserts ADS and ECS to indicate that the memory cycle is starting The ad- dress ...
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Bus Interface (Continued Memory Cycle for BMODE 0 Asynchronous e Mode On the rising edge of T1 the SONIC-16 asserts ADS and ECS to indicate that the memory cycle is starting The ad- dress ...
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Bus Interface (Continued) During read cycles ( Figures 5-16 and 5-17 ) data (D15–D0) is latched at the falling edge of T2 and DS is asserted at the falling edge of T1 For write cycles ( Figures 5-18 ...
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Bus Interface (Continued Bus Exceptions (Bus Retry) The SONIC-16 provides the capability of handling errors during the execution of the bus cycle ( Figure 5-20 ) The system asserts BRT (bus retry) to force the ...
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Bus Interface (Continued) FIGURE 5-21 Register Read BMODE FIGURE 5-22 Register Write BMODE 11722 – 11722 – 48 ...
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Bus Interface (Continued Slave Cycle for BMODE 0 e The system accesses the SONIC-16 by driving SAS CS SWR and These signals will be sampled each k l bus cycle but ...
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Bus Interface (Continued) FIGURE 5-24 Register Write BMODE FIGURE 5-25 On-Chip Memory Arbiter 11722 – 11722 – 51 ...
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Bus Interface (Continued On-Chip Memory Arbiter For applications which share the buffer memory area with the host system (shared-memory applications) the SONIC- 16 provides a fast on-chip memory arbiter for efficiently re- solving accesses between ...
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Bus Interface (Continued) 13 PCOMP will not be asserted (DCR2) 14 Packets will be accepted (not rejected) on CAM match (DCR2) A software reset immediately terminates DMA operations and future interrupts The chip is put into an idle ...
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Network Interfacing (Continued) 69 ...
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Network Interfacing (Continued) External ENDEC When EXT 1 the internal ENDEC is by- e passed and the signals are provided directly to the user Since SONIC-16’s on-chip ENDEC is the same as Nation- al’s DP83910 Serial Network Interface ...
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Network Interfacing (Continued) FIGURE 6 4 Crystal Connection to the SONIC-16 (see text) Note 1 The X1 pin is not guaranteed to provide a TTL compatible logic output and should not be used to drive any external logic ...
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... AC and DC Specifications Absolute Maximum Ratings If Military Aerospace specified devices are required please contact the National Semiconductor Sales Office Distributors for availability and specifications Supply Voltage ( Input Voltage ( Output Voltage ( OUT DC Specifications Symbol Parameter V Minimum High Level Output Voltage OH V Maximum Low Level Output Voltage ...
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AC and DC Specifications AC Specifications BUS CLOCK TIMING Number Parameter T1 Bus Clock Low Time T2 Bus Clock High Time T3 Bus Clock Cycle Time (Note 2) POWER-ON RESET NON POWER-ON RESET Number Parameter T4 USR 1 ...
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AC and DC Specifications MEMORY WRITE BMODE 0 SYNCHRONOUS MODE (one wait-state shown) e Number Parameter T9 BSCK to Address Valid T10 Address Hold Time from BSCK T11 BSCK to ADS ECS Low T12 BSCK to ADS ECS ...
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AC and DC Specifications MEMORY READ BMODE 0 SYNCHRONOUS MODE (one wait-state shown) e Number Parameter T9 BSCK to Address Valid T10 Address Hold Time from BSCK T11 BSCK to ADS ECS Low T12 BSCK to ADS ECS ...
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AC and DC Specifications MEMORY WRITE BMODE 0 ASYNCHRONOUS MODE e Number Parameter T9 BSCK to Address Valid T10 Address Hold Time from BSCK T11b BSCK to ADS DS ECS Low T12b BSCK to ADS ECS High T13 ...
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AC and DC Specifications MEMORY READ BMODE 0 ASYNCHRONOUS MODE e Number Parameter T9 BSCK to Address Valid T10 Address Hold Time from BSCK T11b BSCK to ADS DS ECS Low T12b BSCK to ADS DS ECS High ...
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AC and DC Specifications MEMORY WRITE BMODE 1 SYNCHRONOUS MODE (one wait-state shown) e Number Parameter T9 BSCK to Address Valid T10 Address Hold Time from BSCK T11a BSCK ECS Low T12a BSCK to AS ...
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AC and DC Specifications MEMORY READ BMODE 1 SYNCHRONOUS MODE (one wait-state shown) e Number Parameter T9 BSCK to Address Valid T10 Address Hold Time from BSCK T11a BSCK ECS Low T12a BSCK to AS ...
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AC and DC Specifications MEMORY WRITE BMODE 1 ASYNCHRONOUS MODE e Number Parameter T9 BSCK to Address Valid T10 Address Hold Time from BSCK T11a BSCK ECS Low T12a BSCK to AS ECS High T13a ...
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AC and DC Specifications MEMORY READ BMODE 1 ASYNCHRONOUS MODE e Number Parameter T9 BSCK to Address Valid T10 Address Hold Time from BSCK T11a BSCK ECS Low T12a BSCK to AS ECS High T13a ...
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AC and DC Specifications BUS REQUEST TIMING BMODE 0 e Number Parameter T43 BSCK to HOLD High (Note 2) T44 BSCK to HOLD Low (Note 2) T45 HLDA Asynchronous Setup Time to BSCK T46 HLDA Deassert Setup Time ...
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AC and DC Specifications BUS REQUEST TIMING BMODE 1 e Number T45a BG Asynchronous Setup Time to BSCK T47 BSCK Low to BR Low T48 BSCK Low to BR TRI-STATE (Note 4) T49 BSCK High to BGACK Low ...
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AC and DC Specifications BUS RETRY Number Parameter T41 Bus Retry Synchronous Setup Time to BSCK (Note 3) T41a Bus Retry Asynchronous Setup Time to BSCK (Note 3) T42 Bus Retry Hold Time from BSCK (Note 2) T43 ...
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AC and DC Specifications MEMORY ARBITRATION SLAVE ACCESS Number Parameter T56 CS Low Asynch Setup to BSCK (Note 2) T57 CS High Asynch Setup to BSCK T58 MREQ Low Asynch Setup to BSCK (Note 2) T59 MREQ High ...
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AC and DC Specifications REGISTER READ BMODE 0 (Note 1) e Number Parameter T56 CS Asynch Setup to BSCK (Note 4) T60 MREQ SMACK Low (Notes T62 SAS Assertion before CS (Note ...
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AC and DC Specifications REGISTER WRITE BMODE 0 (Note 1) e Number Parameter T56 CS Asynch Setup to BSCK (Note 4) T60 MREQ SMACK Low (Notes T62 SAS Assertion before CS (Note ...
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AC and DC Specifications REGISTER READ BMODE 1 (Note 1) e Number Parameter T56 CS Asynch Setup to BSCK (Note 5) T60 MREQ SMACK Low (Notes T62 SAS Assertion before CS (Note ...
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AC and DC Specifications REGISTER WRITE BMODE 1 (Note 1) e Number Parameter T56 CS Asynch Setup to BSCK (Note 5) T60 MREQ SMACK Low (Notes T62 SAS Assertion before CS (Note ...
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AC and DC Specifications ENDEC TRANSMIT TIMING (INTERNAL ENDEC MODE) Number Parameter T87 Transmit Clock High Time (Note 1) T88 Transmit Clock Low Time (Note 1) T89 Transmit Clock Cycle Time (Note 1) T95 Transmit Output Delay (Note ...
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AC and DC Specifications ENDEC RECEIVE TIMING (INTERNAL ENDEC MODE) ENDEC COLLISION TIMING Number Parameter T102 Receive Clock Duty Cycle Time (Note 1) T105 Carrier Sense on Time T106 Data Acquisition Time T107 Receive Data Output Delay T108 ...
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AC and DC Specifications ENDEC-MAC SERIAL TIMING FOR RECEPTION (EXTERNAL ENDEC MODE) Number Parameter T118 Receive Clock High Time T119 Receive Clock Low Time T120 Receive Clock Cycle Time T121 RXD Setup to RXC T122 RXD Hold from ...
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AC and DC Specifications ENDEC-MAC SERIAL TIMING FOR TRANSMISSION (COLLISION) Number Parameter T135 Collision Detect Width (Note 1) T136 Delay from Collision T137 Jam Period Note 1 tcyc transmit clock e (Continued) Min 11722 ...
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AC Timing Test Conditions All specifications are valid only if the mandatory isolation is employed and all differential signals are taken the AUI side of the pulse transformer Input Pulse Levels (TTL CMOS) Input Rise ...
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95 ...
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