DP83959 National Semiconductor, DP83959 Datasheet
DP83959
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DP83959 Summary of contents
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... DP83959 8-Port Lite Ethernet Repeater Interface Controller General Description The DP83959 8-Port Lite Ethernet Repeater Interface Controller (LERIC8 single chip solution for unman- aged 10BASE-T Ethernet repeater (hub) products. By inte- grating electronics needed to support eight 10BASE-T ports, a full level/drive compatible AUI port for a backbone ...
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Block Diagram DataSheet4U.com 4 DataSheet U .com DataSheet4U.com 2 www.national.com ...
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Table of Contents 1.0 System Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 ...
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... PQFP 144 Top View 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 DataSheet4U.com Order Number DP83959VUL See NS Package Number VUL160A TX8- 79 TX8 GND_P8 VCC_P8 76 RX8 RX8+ 73 RX0- RX0+ 72 CD0- ...
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... This output should be connected directly to the AUI isolation transformer. 69 AUI Transmit -: The AUI transmit path includes National Semiconductor's patented low power dissipation differential drivers that do not need external load resistors. This output should be connected directly to the AUI isolation transformer. ...
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Pin Descriptions The values of the resistor/capacitor parallel source imped- ance matching networks connected to each of the 10BASE-T transmit outputs will depend upon PCB layout factors (such as track length, width, route etc.) and will have to ...
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... Pin Descriptions 4.3 STATUS LED INTERFACE All the DP83959's direct drive LED outputs can drive up to 14mA maximum. The LED outputs are intended to drive an external LED with a series current limiting resistor. The Par- tition/Link OK LED outputs can sink or source current and are thus suitable for driving single or bi-color LEDs directly ...
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Pin Descriptions Signal Name Type P/L_6A O (14mA P/L_6B max.) P/L_7A O (14mA P/L_7B max.) P/L_8A O (14mA P/L_8B max.) /TRAF1 O (14mA max.) /TRAF2 O (14mA max.) /TRAF3 O (14mA max.) /TRAF4 O (14mA max.) /TRAF5 O ...
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Pin Descriptions Signal Name Type /PART0 O (14mA max.) /GCOL O (14mA max.) /GACT O (14mA max.) 4.4 INTER-LERIC BUS INTERFACE Signal Name Type /ACKI /ACKO IRD I/O /IRE I/O IRC I/O /COLN I/O DataSheet4U.com 4 DataSheet U ...
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Pin Descriptions Signal Name Type /ACTN I/O (O.D.) /ANYXN I/O (O.D.) 4.5 CLOCK INTERFACE Signal Name Type X_IN X_OUT DataSheet4U.com 4 DataSheet U .com (Continued) Pin # 48 Activity on Port N: The LERIC8 asserts this signal when ...
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Pin Descriptions 4.6 REGISTER/CONFIGURATION INTERFACE Signal Name Type RA4 I/O RA3 RA2 RA1 RA0 D3 I /RD /WR /READY /STR DFS BUFEN /MLOAD DataSheet4U.com 4 DataSheet U .com (Continued) Pin # 63 Register Address [4:0]: ...
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... Normal Analog Transmit Data - Transmit outputs are normal 10BASE- Pre-Filter TTL Transmit Data - Transmit outputs become TTL level 40, No Connect: These pins are not connected internally to the DP83959. They 41, 42, should be connected directly to the PCB ground plane. This will help decrease 80, 81, the thermal resistance between the device and its environment ...
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... LERIC8 0.1 F capacitor as close to the pins as possible. 0.01µF 64 4.8.7 VDD_PLL The DP83959's digital core logic power supply pins should be decoupled in pairs with 0.1 F capacitors as close to the pins as possible. The digital power and ground pin pairs are 65 GND_PLL as follows: 13 ...
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... TW1 to TW6) are fulfilled. Some of the major functions of the MSM and Timers are shown in Table 1. The MSM is the heart of the DP83959. It controls the opera- tion of most of the functional blocks and performs the major- ity of the data and collision propagation operations as defi ...
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... Functional Description The DP83959 has a 32 bit elasticity buffer (FIFO) in the transmit path prior to the transmit de-multiplexer. This en- ables the DP83959 to synchronize data packets to its own local clock prior to transmission and regenerate preamble as required. Soon after the network segment receiving the data packet has been identifi ...
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... The rising edge of the selected reset signal is used to start the 1 second LED test operation power-on test feature, the DP83959 will assert all sin- gle ended LED outputs, the DP83955/6 compatible LED outputs and the 'B' outputs of the bi-color LED outputs. The ...
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... Figure 5. DP83959 Direct Drive LED Connections +5V www.national.com ...
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... Figure 6. This logic is repeated for each of the 10BASE-T ports ('n' in Figure 6 refers to any of ports 1 through 8). The DP83959 bi-color LED outputs use two pins each, so that ei- ther end of a two-lead bi-color LED may be driven high or low in order to achieve the required functionality. Two-lead bi-color LEDs require only the addition of a single series cur- rent limiting resistors ...
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... AUI PORT 0 The DP83959 LERIC8 has a single AUI port that uses the standard 3 differential pairs of signal connections. The AUI receiver input pairs (RX0+/- and CD0+/-) require external line termination (78 balanced termination). The AUI trans- ...
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... Functional Description Pin Mnemonic D0 ACOL D1 AREC D2 JAB D3 APART RA[4:0] - /STR - DP83959 LERIC8 RA0 60 RA1 61 RA2 62 RA3 63 RA4 36 STR DataSheet4U.com 4 DataSheet U .com (Continued) Table 4 LERIC8 Min Mode LED Function Min Mode Function Any Collision: Asserted when a collision occurs on any of this LERIC8's ports. ...
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... Functional Description DP83959 LERIC8 TXn+ TXn- RXn+ RXn- DataSheet4U.com 4 DataSheet U .com (Continued) DP83959 LERIC8 1:1 TX0+ TX0- 1:1 RX0+ 39.2 ±1% 39.2 ±1% RX0- 0.01µF 1:1 CD0+ 39.2 ±1% 39.2 ±1% CD0- 0.01µF +12V DataSheet4U.com Fuse Figure 8. Typical AUI Port Connection ...
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LERIC8 Registers 6.1 REGISTER ADDRESS MAP The LERIC8's register address map is shown below. Since the data path is only a nibble wide interface, each register has two addresses, with the most significant address bit (RA4) used to ...
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LERIC8 Registers 6.2 LERIC8 STATUS REGISTER Address: RA4 - RA0 0 0000 - lower nibble 1 0000 - upper nibble Bit Bit Name D0 /ACOL D1 /AREC D2 /JAB D3 /APART D4 Reserved D5 Reserved D6 Reserved D7 ...
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LERIC8 Registers 6.3 PORT 0 (AUI) STATUS/CONFIGURATION REGISTER Address: RA4 - RA0 0 0001 - lower nibble 1 0001 - upper nibble Bit Bit Name D0 Reserved D1 /COL D2 /REC D3 /PART D4 Reserved D5 Reserved D6 ...
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LERIC8 Registers 6.4 PORTS 1-8 (10BASE-T) STATUS/CONFIGURATION REGISTERS Address: RA4 - RA0 0 0010 to 0 1001 - lower nibble 1 0010 to 1 1001 - upper nibble Bit Bit Name D0 /GDLNK D1 /COL D2 /REC D3 ...
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... CASCADING Figure 10 shows the connection diagram for using 3 DP83959s in a single repeater. Most of the inter-LERIC bus is tied together. /ACKO of one device is connected to /ACKI of the next one. /ACKI on one end of the chain is tied high, while /ACKO on the other end is a no-connect. ...
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DC Specifications Absolute Maximum Ratings Supply Voltage ( Input Voltage ( Output Voltage (V OUT Power Dissipation ( Storage Temperature Range (T Lead Temp (Soldering, 10 sec) L ...
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Switching Characteristics 9.1 PORT ARBITRATION / Number Symbol T1 ackilackol T2 ackihackoh Note: Timing valid with no receive or collision activities. 9.2 RECEIVE - AUI PORT Receive activity propagation ...
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Switching Characteristics 9.3 RECEIVE - 10BASE-T PORTS Receive activity propagation start up and end delays for 10BASE-T ports Number Symbol T3t rxaackol T4t rxiackoh T5t rxaactnl ...
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Switching Characteristics 9.5 TRANSMIT - 10BASE-T PORTS Receive activity propagation start up and end delays 10BASE-T ports. CLOCK / Number Symbol T15t actnltxa T16t clkitxa Note: /ACKI assumed high. 9.6 COLLISION - ...
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Switching Characteristics 9.6.2 Receive Collisions Number Symbol T32a cdacolna T33a cdicolni T39 colnljs T40 colnhje Note 1: Reception ended before /COLN goes high. 9.7 COLLISION - 10BASE-T PORTS Collision ...
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Switching Characteristics 9.8 COLLISION - ALL PORTS - INTER-LERIC BUS / Number Symbol T34 anylmin T35 anyhtxai T38 anylsj 9.9 COLLISION - ALL PORTS - ONE ...
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Switching Characteristics 9.10 RESET / MLOAD ** / MLOAD_INT /MLOAD_INT is the internal signal which is delayed 5 cycles from the external /MLOAD signal Number Symbol ...
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Switching Characteristics 9.12 REGISTER READ / T89 RA( 4:0 ) (address (data Number Symbol T80 rdadrs T81 rdadrh T82 rdlbufl T83 rdhbufh T84 ...
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Switching Characteristics 9.13 REGISTER WRITE / T99 RA( 4:0 ) (address) D( 3:0 ) (data Number Symbol T90 wradrs T91 wradrh T92 wrlbufl T93 wrhbufh T94 wradatv ...
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Switching Characteristics 9.14 INTER-LERIC BUS (PACKET OUTPUT Number Symbol T101 ircoh T102 ircol T103 ircoc T105 actnolireol T106 ireolirca T107 irdov T108 irdos ...
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... GENERAL TEST CONDITIONS All AUI specifications are valid only if the mandatory isolation transformer is employed and all differential signals are mea- sured at the AUI connector (not at the DP83959 LERIC8 di- rectly). Input Pulse Levels (TTL/CMOS) Input Rise and Fall Times (TTL/CMOS) ...
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... DataSheet4U.com Molded Plastic Quad Flat Package, JEDEC Order Number DP83959VUL NS Package Number VUL160A 2. A critical component is any component of a life support device or system whose failure to perform can be rea- sonably expected to cause the failure of the life support device or system affect its safety or effectiveness ...