HDMP-0482 Hewlett-Packard, HDMP-0482 Datasheet

HDMP-0482

Manufacturer Part Number

HDMP-0482

Description

Manufacturer

Hewlett-Packard

Datasheet

1.HDMP-0482.pdf (12 pages)

Available stocks

Company

Part Number

Manufacturer

Quantity

Price

Company:

Bonase Electronics (HK) Co., Limited

Part Number:

HDMP-0482

Manufacturer:

AVAGO

Quantity:

Current page: 1 of 12
Download datasheet (172Kb)

Description

The HDMP-0482 is an Octal Cell

Port Bypass Circuit (PBC) with

Clock and Data Recovery (CDR)

and data valid detection capabil-

ity included. This device mini-

mizes part count, cost and jitter

accumulation while repeating

incoming signals. Port Bypass

Circuits are used in hard disk

arrays constructed in Fibre

Channel Arbitrated Loop

(FC-AL) configurations. By using

Port Bypass Circuits, hard disks

may be pulled out or swapped

while other disks in the array are

available to the system.

A Port Bypass Circuit (PBC)

consists of multiple 2:1 multiplex-

ers daisy chained along with a

CDR. Each port has two modes of

operation: “disk in loop” and

“disk bypassed”. When the “disk

in loop” mode is selected, the loop

goes into and out of the disk drive

at that port. For example, data

goes from the HDMP-0482’s

TO_NODE[n]± differential output

pins to the Disk Drive Transceiver

IC’s (e.g. an HDMP-1636A) Rx±

differential input pins. Data from

the Disk Drive Transceiver IC’s

Tx± differential outputs goes to

CAUTION: As with all semiconductor ICs, it is advised that normal static precautions

be taken in the handling and assembly of this component to prevent damage and/or

degradation which may be induced by electrostatic discharge (ESD).

Agilent HDMP-0482

Octal Cell Port Bypass Circuit

with CDR and Data Valid Detection

Data Sheet

the HDMP-0482’s FM_NODE[n]±

differential input pins. When the

“disk bypassed” mode is selected,

the disk drive is either absent or

non-functional and the loop

bypasses the hard disk.

The “disk bypassed” mode is

enabled by pulling the BYPASS[n]-

pin low. Leave BYPASS[n]-

floating to enable the “disk in

loop” mode. HDMP-0482’s may be

cascaded with other members of

the HDMP-04XX/HDMP-05XX

family through the FM_NODE and

TO_NODE pins to accommodate

any number of hard disks. The

unused cells in this PBC may be

bypassed by using pulldown

resistors on the BYPASS[n]- pins

for these cells.

An HDMP-0482 may also be used

as eight 1:1 buffers, one with a

CDR and seven without. For

example, an HDMP-0482 may be

placed in front of a CMOS ASIC

to clean the jitter of the outgoing

signal (CDR path) and to better

read the incoming signal (non-

CDR path). In addition, the

HDMP-0482 may be configured as

four 2:1 multiplexers or as four

1:2 buffers.

Features

• Supports 1.0625 GBd fibre channel

• Supports 1.25 GBd Gigabit Ethernet

• Octal cell PBC/CDR in one package

• CDR location determined by choice

• Amplitude valid detection on

• Data valid detection on

• Equalizers on all inputs

• High speed LVPECL I/O

• Buffered Line Logic (BLL) outputs

• 1.09 W typical power at Vcc=3.3V

• 64 Pin, 14 mm, low cost plastic QFP

Applications

• RAID, JBOD, BTS cabinets

• Four 2:1 muxes

• Four 1:2 buffers

• 1 = > N gigabit serial buffer

• N = > 1 gigabit serial mux

operation

(GE) operation

of cable input/output

FM_NODE[7] input

FM_NODE[0] input

– Run length violation detection

– Comma detection

– Configurable for both single-

(no external bias resistors

required)

package

frame and multi-frame detection

HDMP-0482

Related parts for HDMP-0482

HDMP-0482 Summary of contents

Page 1

... Description The HDMP-0482 is an Octal Cell Port Bypass Circuit (PBC) with Clock and Data Recovery (CDR) and data valid detection capabil- ity included. This device mini- mizes part count, cost and jitter accumulation while repeating incoming signals. Port Bypass Circuits are used in hard disk ...

Page 2

... FM_NODE[0]_DV MODE_VDD BYPASS0 Figure 1. Block Diagram of HDMP-0482. HDMP-0482 Block Diagram CDR The Clock and Data Recovery (CDR) block is responsible for frequency and phase locking onto the incoming serial data stream and resampling the incoming data based on the recovered clock. An automatic locking ...

Page 3

... Buffered Line Logic (BLL) circuit that has on-chip source termination external bias resistors are required. The BLL Outputs on the HDMP-0482 are of equal strength and can drive in excess of 120 inches of FR-4 PCB trace. Unused outputs should not be left unconnected. Ideally, ...

Page 4

... FM_NODE[0]_DV BYPASS0 Figure 2. Block Diagram of HDMP-0482, MODE_VDD is HIGH FM_NODE[0]_DV Figure 3. Block Diagram of HDMP-0482, MODE_VDD is LOW CDR CDR ...

Page 5

... FM_NODE[7]_AV 14 FM_NODE[0]- 15 FM_NODE[0 Figure 4. HDMP-0482 Package Layout and Marking, Top View. nnnn-nnn = wafer lot - build number; Rz.zz = Die Revision Supplier Code; YYWW = Date Code (YY = year work week); COUNTRY = country of manufacture (on back side). Table 2. I/O Type Definitions. I/O Type Definition I-LVTTL LVTTL Input ...

Page 6

... Table 3. Pin Definitions for HDMP-0482. Pin Name Pin Pin Type TO_NODE[0]+ 20 HS_OUT TO_NODE[0]- 19 TO_NODE[1]+ 23 TO_NODE[1]- 22 TO_NODE[2]+ 32 TO_NODE[2]- 31 TO_NODE[3]+ 35 TO_NODE[3]- 34 TO_NODE[4]+ 44 TO_NODE[4]- 43 TO_NODE[5]+ 47 TO_NODE[5]- 46 TO_NODE[6]+ 57 TO_NODE[6]- 56 TO_NODE[7]+ 60 TO_NODE[7]- 59 FM_NODE[0]+ 16 HS_IN FM_NODE[0]- 15 FM_NODE[1]+ 26 FM_NODE[1]- 25 FM_NODE[2]+ 29 FM_NODE[2]- 28 FM_NODE[3]+ 38 FM_NODE[3]- 37 FM_NODE[4]+ 41 FM_NODE[4]- 40 FM_NODE[5]+ 51 FM_NODE[5]- 50 FM_NODE[6]+ ...

Page 7

... Table 3, continued. Pin Definitions for HDMP-0482. Pin Name Pin Pin Type GND VCCA 8 S VCCHS[0, VCCHS[2, VCCHS[ VCCHS[ VCCHS[6, VCC HDMP-0482 Absolute Maximum Ratings T =25° C, except as specified. Operation in excess of any of these conditions may result in permanent a damage to this device. T refers to the ambient temperature for the board upon which the parametric a measurements were taken ...

Page 8

... OP,HS_OUT HDMP-0482 Power Dissipation 0°C to +70° Symbol Parameter P Power Dissipation D HDMP-0482 Output Jitter Characteristics, T Symbol Parameter RJ Random Jitter at TO_NODE pins (1 sigma rms) DJ Deterministic Jitter at TO_NODE pins (pk-pk) Please refer to Figures 6 and 7 for jitter measurement setup information. HDMP-0482 Locking Characteristics, T Parameter ...

Page 9

... Figure 7. Setup for Measurement of Deterministic Jitter. 9 HDMP-0482 BYPASS[0]- +/- FM_NODE[0] BYPASS[1:4]- REFCLK +/- TO_NODE[0] 1.4V 2 106.25 MHz Ch 1/2 HP 83480A Digital Trigger Communication Analyzer HDMP-0482 BYPASS[0]- +/- FM_NODE[0] BYPASS[1:4]- REFCLK +/- TO_NODE[0] 1.4V 2 106.25 MHz Ch 1/2 HP 83480A Digital Trigger Communication 53.125 MHz Analyzer N/C 1 KΩ ...

Page 10

O-LVTTL Vcc ESD Protection GND Figure 8. O_LVTTL and I_LVTTL Simplified Circuit Schematic. HS_OUT 75 Ohms TO_NODE[n]+ TO_NODE[n]- GND ESD Protection Figure 9. HS_OUT and HS_IN Simplified Circuit Schematic. Note: FM_NODE[n] inputs should never be connected to ground as permanent ...

Page 11

... HDMP-0482 14.00 ±0.10 Tolerance 11 = 0°C to 85° 3.15V to 3.45V C CC Unit Typ. Max. °C/W 9.5 — for these devices is 39.4°C/W for the HDMP-0482 (θ where the power being D Details Plastic 85% Tin, 15% Lead 300 – 800 micro-inches 0.20 mm max. ...

Page 12

... India, Australia, New Zealand: (65) 6755 1939 Japan: (+81 3) 3335-8152(Domestic/International), or 0120-61-1280(Domestic Only) Korea: (65) 6755 1989 Singapore, Malaysia, Vietnam, Thailand, Philippines, Indonesia: (65) 6755 2044 Taiwan: (65) 6755 1843 Data subject to change. Copyright © 2003 Agilent Technologies, Inc. Obsoletes 5988-7140EN June 16, 2003 5988-9758EN HDMP-0482 VCC VCC ...

Related keywords

HDMP-0482 datasheet
HDMP-0482 data sheet
HDMP-0482 pdf datasheet
HDMP-0482 component
HDMP-0482 part
HDMP-0482 distributor
HDMP-0482 RoHS
HDMP-0482 datasheet download