PC87317 National Semiconductor, PC87317 Datasheet
PC87317
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PC87317 Summary of contents
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... PC97 Hardware Design Guide . It features a Controller/Extender that is fully compli- ant with Advanced Configuration and Power Interface (AC- PI) Revision 1.0 requirements. Note: All references to the PC87317VUL in this document also refer to the PC97317VUL, unless otherwise specified. References which are applicable to the PC97317VUL only are italicized. ...
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... Highlights — Customizing by using the PC87323VUL, which in- cludes a RAM-based KBC development plat- form for keyboard PC87317VUL An RTC that has: — A modifiable address that is referenced by a 16-bit programmable register ® — 13 IRQ options, with programmable polarity in ® — DS1287, MC146818 and PC87911 compatibility and — ...
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A Fail-safe event occurs (power-save mode detected but the system is hung up) — Software turns power off — Any one of 10 programmable Power Management trigger events occur Two Serial Ports (UART1 and 2) that provide: — Fully ...
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... Highlights General Purpose I/O Keyboard I/O (GPIO) Interface X1 MR AEN A15-0 D7-0 DTR1/BOUT1 RD WR IOCHRDY ZWS IRQ1 IRQ12-3 IRQ15-14 DRQ3-0 DACK3-0 PC87317VUL TC LED DTR2/BOUT2 XDRD XDCS XD7-0 PD7-0 SLIN/ASTRB STB/WRITE AFD/DSTRB INIT ACK ERR SLCT PE BUSY/WAIT BADDR1,0 CFG1,0 SELCS X1C ...
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... THE CONFIGURATION REGISTERS ....................................................................................... 29 2.3.1 Standard Plug and Play (PnP) Register Definitions .................................................... 30 2.3.2 Configuration Register Summary ................................................................................ 33 2.4 CARD CONTROL REGISTERS ................................................................................................ 37 2.4.1 PC87317 SID Register ................................................................................................ 37 2.4.2 PC97317 SID Register ................................................................................................ 37 2.4.3 SuperI/O Configuration 1 Register (SIOC1) ................................................................ 37 2.4.4 SuperI/O Configuration 2 Register (SIOC2) ................................................................ 38 2.4.5 Programmable Chip Select Configuration Index Register ........................................... 38 2 ...
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... EXTERNAL I/O INTERFACES .................................................................................................. 50 3.4.1 Keyboard and Mouse Interface ................................................................................... 50 3.4.2 General Purpose I/O Signals ....................................................................................... 50 3.5 INTERNAL KBC - PC87317VUL INTERFACE .......................................................................... 51 3.5.1 The KBC DBBOUT Register, Offset 60h, Read Only .................................................. 52 3.5.2 The KBC DBBIN Register, Offset 60h (F1 Clear) or 64h (F1 Set), Write Only ............ 52 3.5.3 The KBC STATUS Register ........................................................................................ 52 3 ...
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The ONCTL Flip-Flop and Signal ................................................................................ 62 4.4.2 Entering Power States ................................................................................................. 65 4.4.3 System Power-Up and Power-Off Activation Event Description .................................. 67 4.5 APC REGISTERS ...................................................................................................................... 69 4.5.1 APC Control Register 1 (APCR1) ................................................................................ 70 4.5.2 APC Control ...
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APC Register Bitmaps ................................................................................................. 84 4.9 REGISTER BANK TABLES ....................................................................................................... 89 The Digital Floppy Disk Controller (FDC) (Logical Device 3) 5.0 5.1 FDC FUNCTIONS ..................................................................................................................... 92 5.1.1 Microprocessor Interface ............................................................................................. 92 5.1.2 System Operation Modes ............................................................................................ 92 5.2 DATA ...
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The MODE Command ............................................................................................... 119 5.7.8 The NSC Command .................................................................................................. 121 5.7.9 The PERPENDICULAR MODE Command ............................................................... 121 5.7.10 The READ DATA Command ..................................................................................... 122 5.7.11 The READ DELETED DATA Command .................................................................... 124 5.7.12 The READ ID Command ........................................................................................... ...
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Hardware Operation .................................................................................................. 145 6.5 ECP MODE REGISTERS ........................................................................................................ 145 6.5.1 Accessing the ECP Registers .................................................................................... 146 6.5.2 Second Level Offsets ................................................................................................ 146 6.5.3 ECP Data Register (DATAR) ..................................................................................... 147 6.5.4 ECP Address FIFO (AFIFO) Register ....................................................................... 147 6.5.5 ...
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SHARP-IR MODE – DETAILED DESCRIPTION ..................................................................... 163 7.6 SIR MODE – DETAILED DESCRIPTION ................................................................................ 163 7.7 CONSUMER-IR MODE – DETAILED DESCRIPTION ............................................................ 164 7.7.1 Consumer-IR Transmission ....................................................................................... 164 7.7.2 Consumer-IR Reception ............................................................................................ 164 7.8 FIFO TIME-OUTS .................................................................................................................... 165 7.8.1 ...
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Register .................................................................................................. 183 7.16.3 Infrared Control Register 2 (IRCR2) .......................................................................... 183 7.16.4 Reserved Registers ................................................................................................... 183 7.17 BANK 6 – INFRARED PHYSICAL LAYER CONFIGURATION REGISTERS ......................... 183 7.17.1 Infrared Control Register 3 (IRCR3) .......................................................................... 183 7.17.2 Reserved Register ...
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Extended Control Register 1 (EXCR1) ...................................................................... 208 8.7.3 Line Control Register (LCR) and Bank Select Register (BSR) .................................. 209 8.7.4 Extended Control and Status Register 2 (EXCR2) .................................................... 209 8.7.5 Reserved Register ..................................................................................................... 209 8.7.6 TX_FIFO Current Level Register ...
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ACPI Support Register .............................................................................................. 225 10.3 POWER MANAGEMENT REGISTER BITMAPS .................................................................... 226 X-Bus Data Buffer 11.0 The Internal Clock 12.0 12.1 THE CLOCK SOURCE ............................................................................................................ 230 12.2 THE INTERNAL ON-CHIP CLOCK MULTIPLIER ................................................................... 230 12.3 SPECIFICATIONS ................................................................................................................... 230 12.4 ...
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Group 25 .................................................................................................................... 242 14.2.26 Group 26 .................................................................................................................... 243 14.2.27 Group 27 .................................................................................................................... 243 14.2.28 Group 28 .................................................................................................................... 243 14.3 AC ELECTRICAL CHARACTERISTICS .................................................................................. 244 14.3.1 AC Test Conditions 14.3.2 Clock ...
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... GPIO16/PME1 GPIO17/WDO GPIO20/IRSL1/ID1 GPIO21/IRSL0/IRSL2/ID2 GPIO22/POR 160 GPIO23/RING 1 5 www.national.com Signal/Pin Connection and Description 110 105 100 95 PC87317VUL PlasticQuad Flatpack (PQFP), EIAJ Order Number PC87317VUL/PC97317VUL NS Package Number VUL160A GPIO24/IRRX1 80 GPIO37/IRRX2/IRSL0/ID0 IRSL1/ID1/XD7 IRSL2/SELCS/GPIO21/XD6 GPIO27/XD5 75 GPIO26/XD4 GPIO25/XD3 GPIO24/XD2 CS2/XD1 CS1/XD0/CSOUT-NSC-Test 70 XDRD/ID3 RING/XDCS LED/CS0 ...
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... SIGNAL/PIN DESCRIPTIONS TABLE 1-1 "Signal/Pin Description Table" lists the signals of the PC87317VUL in alphabetical order and shows the pin(s) associated with each. TABLE 1-2 "Multiplexed X-Bus Data Buffer (XDB) Pins" on page 25 lists the X-Bus Data Buffer (XDB) signals that are multiplexed and TABLE 1-6 " ...
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... TRI-STATE unless V applied. CS1 is multiplexed with CSOUT-NSC-Test/XD0. CS2 is multiplexed with XD1. Output Chip Select Read Output, NSC-Test – National Semiconductor test output. This is an open-drain output signal. Group 21 This signal is multiplexed with CS1 and XD0. Input UART1 and UART2 Clear to Send – ...
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Signal/Pin Pin Module Name Number DRQ3-0 55-52 ISA-Bus DSKCHG 99 FDC DSR2,1 143, 133 UART1, UART2 DSTRB 119 Parallel Port DTR2,1 144, 134 UART1, UART2 ERR 116 Parallel Port 156-154 General GPIO17-15 Purpose GPIO14 153 GPIO13,12 152,151 GPIO11 150 GPIO10 ...
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Signal/Pin Pin Module Name Number GPIO37-30 79, General Purpose 148-145, 143-141 HDSEL 92 FDC ID3-0 70, 158, UART2 78 or 157, 79 INDEX 97 FDC INIT 117 Parallel Port IOCHRDY 32 ISA-Bus IRQ1 36 ISA-Bus IRQ5-3 39-37 IRQ12-6 47-41 IRQ15,14 ...
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Signal/Pin Pin Module Name Number IRTX 81 UART2 KBCLK 102 KBC KBDAT 103 KBC LED 68 APC MCLK 104 KBC MDAT 105 KBC MR 51 ISA-Bus MSEN1,0 83, 82 FDC MTR1,0 86, 85 FDC ONCTL 67 APC P17,16 108, 107 ...
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... SuperI/O Configuration 1 register (index 21h). Group internal pull-up resistor ( resistor for National Semiconductor testing) controls this pin during reset. Do not pull this signal low during reset. This signal is multiplexed with GPIO21, IRSL2 and XD6. Input Serial Input – This input signal receives composite serial data from ...
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Signal/Pin Pin Module Name Number SLCT 114 Parallel Port SLIN 118 Parallel Port SOUT2,1 148, 138 UART1, UART2 STB 112 Parallel Port STEP 91 FDC SWITCH 66 APC TC 35 ISA-Bus TRK0 96 FDC V 64 RTC and BAT APC ...
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Signal/Pin Pin Module Name Number WDATA 89 FDC WDO 156 Power Man- agement WGATE 93 FDC WP 98 FDC WR 34 ISA-Bus WRITE 112 Parallel Port X1 50 Clock X1C 62 RTC X2C 63 RTC XD7,6, 78, 77 X-Bus XD1,0 ...
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Signal/Pin Connection and Description TABLE 1-2. Multiplexed X-Bus Data Buffer (XDB) Pins X-Bus Data Buffer (XDB) Pin Bit 4 of SuperI/O Configuration Register XDCS 70 XDRD 71 XD0 72 XD1 73 XD2 73 XD3 75 XD4 ...
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TABLE 1-5. Infrared/KBC or GPIO/Chip-Select Pin Designation Pin Infrared, KBC, UART2 157 IRSL1/ID1 158 IRSL2/IRSL0/ID2 80 IRRX1 107 P16 145 RI2 79 IRRX2/IRSL0/ID0 106 P12 TABLE 1-6. Pins with a Strap Function During Reset Strap Function BADDR1,0 CFG1,0 SELCS www.national.com ...
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... The Plug and Play soft reset has no effect on the logical de- vices, except for the effect of the Activate registers (index 30h) in each logical device. The PC87317VUL can wake up with the FDC, the KBC and the RTC either active (enabled) or inactive (disabled). The other logical devices and the internal on-chip clock multipli- er wake up inactive (disabled) ...
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... If, during reset, the Base Address 1 (BADDR1) signal is low (0), the Index and Data registers are not accessible imme- diately after reset result, all configuration registers of the PC87317VUL are also not accessible at this time. To access these registers, you must apply the Plug and Play (PnP) ISA protocol. ...
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... The SuperI/O processor does not decode the Parallel Port outside this range. 2.3 THE CONFIGURATION REGISTERS The configuration registers control the setup of the PC87317VUL. Their major functions are to: Identify the chip Enable major functions (such as, the Keyboard Control- ler (KBC) for the keyboard and the mouse, the Real- ...
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Standard Plug and Play (PnP) Register Definitions TABLES 2-5 through 2-10 describe the standard Plug and Play registers. For more detailed information on these TABLE 2-5. Plug and Play (PnP) Standard Control Registers Index Name 00h Set RD_DATA Port ...
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TABLE 2-6. Plug and Play (PnP) Logical Device Control Registers Index Name 0030h Activate For each logical device there is one Activate register that controls whether or not the logical device is active on the ISA bus. This is a ...
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TABLE 2-8. Plug and Play (PnP) Interrupt Configuration Registers Index Name 70h Interrupt Request Read/write value indicating selected interrupt level. Level Select 0 Bits3-0 select the interrupt level used for interrupt 0. A value of 1 selects IRQL 1, a ...
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Configuration Register Summary The tables in this section specify the Index, type (read/write), reset values and configuration register or ac- tion that controls each register associated with each func- tion. When the reset value is not fixed, the table ...
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TABLE 2-13. KBC Configuration Registers for Mouse - Logical Device 1 Index R/W Hard Reset Soft Reset 30h R/W 00h 70h R/W 0Ch 71h R/W 02h 74h R 04h 75h R 04h TABLE 2-14. RTC and APC Configuration Registers - ...
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TABLE 2-16. Parallel Port Configuration Registers - Logical Device 4 Index R/W Hard Reset 30h R/W 00h 31h R/W 00h 60h R/W 02h 61h R/W 78h 70h R/W 07h 71h R/W 00h 74h R/W 04h 75h R 04h F0h R/W ...
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TABLE 2-18. UART1 Configuration Registers - Logical Device 6 Index R/W Hard Reset 30h R/W 00h 31h R/W 00h 60h R/W 03h 61h R/W F8h 70h R/W 04h 71h R/W 03h 74h R 04h 75h R 04h F0h R/W See ...
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... See TABLE 2-24 "The Programmable Chip Select Configuration Registers" on page 43. 2.4.1 PC87317 SID Register This read-only register holds the revision and chip identity number of the chip. The PC87317VUL is identified by the value D0h in this register. PC87317 SID Register ...
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Bit 4 - X-Bus Data Buffer (XDB) Select Select X-bus buffer on the XDB pins. This read only bit is initialized with the CFG1 strap value. See TABLE 2-21 and see also Chapter 11 "X-Bus Data Buffer" on page 229. ...
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Programmable Chip Select Configuration Data Register This read/write register contains the data in the Program- mable Chip Select Configuration register (see Section 2.10 "PROGRAMMABLE CHIP SELECT CONFIGURATION REGISTERS" on page 42) indicated by the Programmable Chip Select Configuration Index ...
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SuperI/O Configuration F Register (SIOCF), Index 2Fh This register is reserved. Must be written with ‘0’s. 2.5 KBC CONFIGURATION REGISTER (LOGICAL DEVICE 0) 2.5.1 SuperI/O KBC Configuration Register This read/write register is reset by hardware to 40h ...
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Drive ID Register This read/write register is reset by hardware to 00h. These bits control bits 5 and 4 of the enhanced TDR register ...
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UART2 AND INFRARED CONFIGURATION REGISTER (LOGICAL DEVICE 5) 2.8.1 SuperI/O UART2 Configuration Register This read/write register is reset by hardware to 02h Configuration Register ...
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TABLE 2-24. The Programmable Chip Select Configuration Registers Second Level Register Name Index 00h CS0 Base Address MSB Register R/W 00h 01h CS0 Base Address LSB Register R/W 00h 02h CS0 Configuration Register 03h Reserved 04h CS1 Base Address MSB ...
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... Second Level Index 06h CS2 Configuration Register, Second Level Index 0Ah General Purpose Scratch Bits GPIO20 or IRSL1 Pin Select GPIO17 or WDO Pin Select GPIO Bank Select 44 SID (In PC87317 Register Reset Index 20h Required Revision ID Chip ID SID (In PC97317 Register Reset Index 20h ...
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Programmable Chip Select Configuration Index Reset Required Index of a Programmable Chip Select Configuration Register Read Only Programmable Chip Select ...
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Reset Required Mask Address Pin A0 Mask Address Pin A1 Mask Address Pin A2 Mask Address Pin A3 Assert Chip Select Signal on Write ...
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... PC87317VUL multi-I/O chip and houses two separate logi- cal devices: a keyboard controller and a mouse controller. The KBC accepts user input from the keyboard or mouse, and transfers this input to the host PC via the common PC87317VUL-PC interface. The KBC is functionally equivalent to the industry standard 8042A keyboard controller, which may serve as a detailed technical reference for the KBC ...
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... These request signals are controlled by the KBC firmware which generates them by manipulating I/O port signals. See Section 3.3.2 "Interrupt Request Signals". The PC87317VUL supports the KBC and handles interac- tions with the PC chip set. In addition to data transfer, these interactions include KBC configuration, activation and sta- tus monitoring ...
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... For details regarding the configuration of each device, refer to TABLES 2-12 "KBC Configuration Registers for Key- board - Logical Device 0" and 2-13 "KBC Configuration Registers for Mouse - Logical Device 1" on page 34 Standard or Open-Collector TTL Driver X1 PC87317VUL FIGURE 3-4. External Clock Connection 49 Interrupt Plug and Polarity Play Matrix (0 = Invert MUX ...
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... Timer Overflow Flag and Timer interrupt operate as in the timer mode. 3.4 EXTERNAL I/O INTERFACES The PC chip set interfaces with the PC87317VUL as illus- trated in FIGURE 3-2 "System Interfaces" on page 48. All data transactions between the KBC and the PC chip set are handled by the PC87317VUL. ...
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... Port Pin PC87317VUL Port Pin 3.5 INTERNAL KBC - PC87317VUL INTERFACE The KBC interfaces internally with the PC87317VUL via three registers: an input (DBBIN), output (DBBOUT) and status (STATUS) register. See FIGURE 3-1 "KBC System Functional Block Diagram" on page 47 and TABLE 3-1 "System Interface Operations". ...
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... The KBC DBBOUT Register, Offset 60h, Read Only The DBBOUT register transfers data from the keyboard controller to the PC87317VUL written to by the key- board controller and read by the PC87317VUL for transfer to the PC. The PC may be notified of the need to read data from the KBC by an interrupt request or by polling the Out- put Buffer Full (OBF) bit (bit 0 of the KBC STATUS register described in Section 3.5.3 " ...
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... Automatic Power-Down switching enables a con- trolled power-down sequence when switched off by the user. The PC87317VUL APC module supports a variety of exter- nal General Purpose Power Management interrupts, giving the user software - selectable input signal definition for each individual input. It maintains a specific Power Management Timer for implementing operational logic and generating the appropriate interrupt request ...
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Real-Time Clock (RTC) and Advanced Power Control (APC) (Logical Device 2) External Clock and Timing Generation The RTC can use one of the following timekeeping input clock options: A 32768 Hz crystal connected externally at the X1C and X2C pins ...
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... Upon first power-on, it resides in bank 1, Index 48h. The register is configured via the CADDR register in bank 2. For more details, see the RTC and APC Registers. 4.1.3 Power Management The host PC and PC87317VUL power is supplied by the system power supply voltage, V DD. "PC87317VUL Power Supplies". A trickle voltage (V ...
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... If an interrupt is not serviced before a second occurrence of the same interrupt condition, the second interrupt event is lost. FIGURE 4-5 "Interrupt/Status Timing" on page 57 illus- trates interrupt and status timing in the PC87317VUL. 4.2 THE RTC REGISTERS The RTC registers can be accessed at any time during non- battery backed operation. The registers are listed in TABLE 4-1 " ...
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Real-Time Clock (RTC) and Advanced Power Control (APC) (Logical Device 2) TABLE 4-3. Divider Chain Control and Bank Selection DV2-0 Selected Configuration Bank Bank 0 Oscillator Disabled Bank 0 Oscillator Disabled ...
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Real-Time Clock (RTC) and Advanced Power Control (APC) (Logical Device 2) Bit 3 - Unused This bit is defined as “Square Wave Enable” by the MC146818 and is not supported by the RTC. This bit is always read as 0. ...
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Real-Time Clock (RTC) and Advanced Power Control (APC) (Logical Device 2) 4.2.5 Date-of-Month Alarm Register (DMAR This register contains the Day-of-Month alarm setting and its “don’t care” enable bits. Upon first power- located at Bank 1, Index 49h ...
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... APC might not detect the second event, i.e., the event will be lost. www.national.com ACPI Compliance The PC87317 supports all the minimum requirements of the ACPI spec (Rev 1.0): Power Management Timer. Power Button. Real Time Clock Alarm. ...
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... TABLE 4-6 "System Power States" on page 62 in- dicates the power-source combinations for each state. No other power-source combinations are valid. In addition, the power sources and distribution for the entire PC system are described in FIGURE 4-2 "PC87317VUL Power Supplies" on page 55. WARNING illegal for V ...
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... Section 4.4.3 on page 67), or the Power Failure state if external power is removed. www.national.com Knowing the system’s state is important for the correct de- tection of the Switch Events. The PC87317 distinguishes between Power On and Power Off as follows: Power State V exists implies power On ...
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Real-Time Clock (RTC) and Advanced Power Control (APC) (Logical Device 2) User software must ensure unused date/time fields are coherent, to ensure the comparison of valid bits gives the correct results. The RING enable bit (bit 3 of APCR2) is ...
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Real-Time Clock (RTC) and Advanced Power Control (APC) (Logical Device 2) APC Inactive V Power On APC Active Initial Values Power Off APC Active Programmed Values V MOAP (Power Failure Bit = 0) 1 CCH (can occur ...
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... GP2_EN0 register can always enable its corresponding event (All registers referred to in this paragraph are in the ACPI Fixed registers). The PC87317 also supports the SMI Command of the AC- PI. Thus, when bit 5 (status) and bit 6 (enable) of the ACPI Support register are '1', POR is asserted (see Power Man- agement registers, Logical Device 8) ...
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Real-Time Clock (RTC) and Advanced Power Control (APC) (Logical Device 2) RTC Alarm Management Global Lock SMI Command Global Lock GPIO 12,13 rising/falling P12 PME2,1 rising/falling IRRX2,1 GPIO10 Restart Stop SWITCH SWITCH Event Type V DD EXISTS RING RI2,1 A ...
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Real-Time Clock (RTC) and Advanced Power Control (APC) (Logical Device 2) 4.4.3 System Power-Up and Power-Off Activation Event Description The APC may activate the host power supply when the fol- lowing “wake-up” events occur: Physical On/Off switch is depressed and ...
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... An event will wake up the system or generate an interrupt, only if its corresponding status and enable bits are set. LED Signal This output signal enables an external LED to be driven di- rectly by the PC87317, and may be programmed to give various responses under various power conditions. Three signal outputs may be selected: High - Impedance (HI-Z) Drive 0 level “ ...
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Real-Time Clock (RTC) and Advanced Power Control (APC) (Logical Device 2) The SCI Signal The SCI interrupt is used to send ACPI relevant notifications to the host Operating System. The following events assert the SCI signal: RTC alarm Power Button ...
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Real-Time Clock (RTC) and Advanced Power Control (APC) (Logical Device 2) The APC registers are not affected by Master Reset. They are initialized to 0 only when power is applied for the first time, i.e., application of one of the ...
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Real-Time Clock (RTC) and Advanced Power Control (APC) (Logical Device 2) See MOAP (bit 4) of APCR1 and APCR6 bit 6,7 for an overriding case. Bit 6 - Switch Off Delay Enable (SODE) 0: ONCTL output pin is deactivated immediately ...
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Real-Time Clock (RTC) and Advanced Power Control (APC) (Logical Device 2) 4.5.5 Wake up Date of Month Register (WDMR) This register contains the Wake up Date of Month settings. Wake up Date-of-Month ...
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Real-Time Clock (RTC) and Advanced Power Control (APC) (Logical Device 2) Bit 5 - RAM Block Write This bit controls writes to bytes 80h-9Fh (00h-1Fh of up- per RAM). 0: This bit has no effect on upper RAM access. 1: ...
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Real-Time Clock (RTC) and Advanced Power Control (APC) (Logical Device 2) TABLE 4-9. GPIO10 Event settings select APCR3 bits Physical trigger condition Low level High level ...
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Real-Time Clock (RTC) and Advanced Power Control (APC) (Logical Device 2) 4.5.12 APC Control Register 5 (APCR5) This register contains the IRRX2,1 event polarity/edge set- tings and configures I/O pin designations. Upon first Power-Up this register is reset to 2Dh. ...
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Real-Time Clock (RTC) and Advanced Power Control (APC) (Logical Device 2) Bits 5-3 -GPIO13 Event Polarity/Edge Select These bits determine the physical conditions that trigger the GPIO13 Event. These bits are unaffected by Master Reset. TABLE 4-16. GPIO13 Event settings ...
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Real-Time Clock (RTC) and Advanced Power Control (APC) (Logical Device 2) 4.5.15 APC Status Register 1 (APSR1) This is read-only register. The bit settings are unaffected by Master Reset Power- ...
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Real-Time Clock (RTC) and Advanced Power Control (APC) (Logical Device 2) 4.6 ACPI FIXED REGISTERS The APCI fixed registers are divided into four groups: PM1 Event registers PM1 Control registers PM TImer registers General Purpose Event registers These registers, their ...
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Real-Time Clock (RTC) and Advanced Power Control (APC) (Logical Device 2) Bit 7 - Wake Status (WAK_STS) This bit is set to 1, when the system is in the suspended state and an enabled Power Management event occurs. Exception to ...
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... FIGURE 4-37. PM1_CNT_HIGH Register Bitmap Bits 0,1 - Reserved Bits 4-2 - Sleep Type (SLP_TYP) These read/write bits do not affect the PC87317. They are implemented only for compliance with the ACPI standard. In the ACPI standard they define the type of suspend mode the system should enter (when the Sleep Enable bit is set to 1). ...
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Real-Time Clock (RTC) and Advanced Power Control (APC) (Logical Device 2) 4.6.8 Power Management Timer Middle Byte Register (PM1_TMR_MID) This is a read-only register. . Power Management Timer Middle Byte Register Power-Up ...
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Real-Time Clock (RTC) and Advanced Power Control (APC) (Logical Device 2) Bit 2 - IRRX1 Status (IRRX1_S) This bit is set to 1, when an IRRX1 event occurs, regard- less of the IRRX1 Enable bit setting (bit 2 of the ...
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... PM1_CNT_LOW register. 4.7.11 SMI Command Register (SMI_CMD), Offset 0Ch This is an 8-bit read/write register. The data held in this reg- ister has no affect on the PC87317. Any write to this register sets bit 5 of the ACPI Support register (see Logical Device 8). This can assert POR. ...
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Real-Time Clock (RTC) and Advanced Power Control (APC) (Logical Device 2) 4.8 RTC AND APC REGISTER BITMAPS 4.8.1 RTC Register Bitmaps Power- Reset Required ...
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Real-Time Clock (RTC) and Advanced Power Control (APC) (Logical Device 2) Wake up Date-of-Month Power- Reset Required Wake up Date of Month Bits “Don’t ...
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Real-Time Clock (RTC) and Advanced Power Control (APC) (Logical Device Power- Reset Required GPIO12 Event Polarity/Edge GPIO13 Event Polarity/Edge select Extended wake-up options ...
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Real-Time Clock (RTC) and Advanced Power Control (APC) (Logical Device Power- Reset Required Century Address Bank Select Power Management 1 Status Low Byte ...
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Real-Time Clock (RTC) and Advanced Power Control (APC) (Logical Device 2) Power Management Timer Middle Power- Reset Required Power Management Timer Middle Byte Power ...
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Real-Time Clock (RTC) and Advanced Power Control (APC) (Logical Device 2) 4.9 REGISTER BANK TABLES TABLE 4-19. Banks 0, 1 and 2 - Common 64-Byte Memory Map Index FUNCTION 00h Seconds 01h Seconds Alarm 02h Minutes 03h Minutes Alarm 04h ...
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Real-Time Clock (RTC) and Advanced Power Control (APC) (Logical Device 2) Register Index Upper RAM 50h Address Port 51h-52h Upper RAM Data 53h Port 54h-7Fh TABLE 4-22. Bank 2 Registers - APC Memory Bank Register Index 00h - 3Fh APC ...
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Real-Time Clock (RTC) and Advanced Power Control (APC) (Logical Device 2) Register Index Month Alarm Address 50h Register Century Address Register 51h 52h-7Fh TABLE 4-23. Available General Purpose Bytes Index Bank 0Eh - 3Fh All 40h - 7Fh Bank 0 ...
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... See Section 10.2.3 "Func- tion Enable Register 1 (FER1)" on page 219. The PC87317 is software compatible with the DP8473 and 82077 Floppy Disk Controllers (FDCs). Upon a power-on reset, the 16-byte FIFO is disabled. Also, the disk interface ...
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... Motor Speed Variation (% of Nominal) Typical Performance at 500 Kbps, FIGURE 5-2. PC87317 Dynamic Window Margin The x axis measures MSV. MSV is translated directly to the actual rate at which the data separator reads data from the disk. In other words, a faster than nominal motor results in a higher data rate ...
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The Digital Floppy Disk Controller (FDC) (Logical Device 3) The controller maximizes the internal digital data separator by implementing a read algorithm that enhances the lock characteristics of the fully digital Phase-Locked Loop (PLL). The algorithm minimizes the effect of ...
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... Therefore, you should make sure that the motor and drive select signals are turned off. If the power to an external clock driving the PC87317 will be independently removed while the FDC is in power-down mode, it must not be done until 2 msec after the LOW PWR option of the FDC MODE command is issued ...
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The Digital Floppy Disk Controller (FDC) (Logical Device 3) When the controller is ready to receive a command byte, the MSR returns a value of 80h (Request for Master (RQM, bit 7) bit is set). The MSR is guaranteed to ...
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The Digital Floppy Disk Controller (FDC) (Logical Device 3) Bit 5 - Step This bit indicates whether or not the head of the Floppy Disk Drive (FDD) should move during a seek operation. Its value is the inverse of the ...
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The Digital Floppy Disk Controller (FDC) (Logical Device 3) TABLE 5-2. Drive and Motor Pin Encoding for Four Drive Configurations and Drive Exchange Support Control Digital Output Signals Register Bits MTR ...
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The Digital Floppy Disk Controller (FDC) (Logical Device 3) Bit 4- Motor Enable 0 If four drives are supported (bit 7 of the SuperI/O FDC Configuration register at index F0h is 1), this bit may control the motor output signal ...
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The Digital Floppy Disk Controller (FDC) (Logical Device 3) Bits 1,0 - Tape Drive Select 1,0 These bits assign a logical drive number to a tape drive. Drive 0 is not available as a tape drive and is reserved as ...
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The Digital Floppy Disk Controller (FDC) (Logical Device 3) Bit 2 - Drive 2 Busy This bit indicates whether or not drive 2 is busy set to 1 after the last byte of the command phase of a ...
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The Digital Floppy Disk Controller (FDC) (Logical Device 3) Track 0 is the default starting track number for precom- pensation. The starting track number can be changed using the CONFIGURE command. TABLE 5-7. Write Precompensation Delays DSR Bits Duration of ...
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The Digital Floppy Disk Controller (FDC) (Logical Device 3) value for THRESH. this gives the system more time to re- spond to a data transfer service request (DRQ for DMA mode or IRQ for interrupt mode). Conversely, a fast system ...
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The Digital Floppy Disk Controller (FDC) (Logical Device 3) 5.3.9 Configuration Control Register (CCR) This write-only register can be used to set the data transfer rate (in place of the DSR) for PC-AT, PS/2 and MicroChan- nel applications. Other applications ...
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The Digital Floppy Disk Controller (FDC) (Logical Device 3) the leading edge of the active low DACK input signal. After the last byte is transferred, an interrupt is generated, indi- cating the beginning of the result phase. During DMA operations, ...
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... Drive Polling Phase National Semiconductor’s FDC supports the polling mode of old 8-inch drives means of monitoring any change in status for each disk drive present in the system. This sup- port provides backward compatibility with software that ex- pects it ...
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The Digital Floppy Disk Controller (FDC) (Logical Device 3) Even if drive polling is disabled, drive stepping and delayed power-down occur in the drive polling phase. The controller checks the status of each drive and, if necessary, it issues a ...
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The Digital Floppy Disk Controller (FDC) (Logical Device 3) Bit 0 - Missing Address Mark This bit indicates whether or not the Floppy Disk Con- troller (FDC) failed to find an address mark in a data field during a read, ...
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The Digital Floppy Disk Controller (FDC) (Logical Device 3) Bit 3 - Scan Satisfied This bit indicates whether or not the value of the data byte from the microprocessor was equal to a byte on the floppy disk during any ...
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The Digital Floppy Disk Controller (FDC) (Logical Device 3) PS/2 Drive Mode Reset 1 1 Required MTR0 MTR1 WGATE RDATA WDATA DR0 Reserved Reserved ...
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The Digital Floppy Disk Controller (FDC) (Logical Device 3) Read Operations, PS/2 Drive Mode Reset Required High Density DRATE0 Status DRATE1 Status Reserved DSKCHG Write Operations 7 ...
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THE FDC COMMAND SET The first command byte for each command in the FDC com- mand set is the opcode byte. The FDC uses this byte to de- termine how many command bytes to expect invalid command ...
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Abbreviations Used in FDC Commands BFR Buffer enable bit set in the MODE command. En- ables open-collector output buffers. BST Burst mode disable control bit set in MODE com- mand. Disables burst mode for the FIFO, if the FIFO ...
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WG Formerly, the Write Gate control bit. Now included in the Group Drive mode Configuration (GDC) bits in the PERPENDICULAR MODE command. WLD Wildcard bit in the MODE command used to enable or disable the wildcard byte (FFh) during scan ...
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Result Phase Byte of Present Track Number (PTR) Drive 0 Byte of Present Track Number (PTR) Drive 1 Byte of Present Track Number (PTR) Drive 2 Byte of Present Track Number (PTR) Drive 3 Step ...
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Command Phase MFM Bytes-Per-Sector Code Sectors per Track Bytes in Gap 3 Data Pattern TABLE 5-10. Typical Values for PC Compatible Diskette Media Bytes in Data ...
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Fifth Command Phase Byte - Bytes in Gap 3 The number of bytes in gap 3 is programmable. The number to program for Gap 3 depends on the data transfer rate and the type of the disk drive. TABLE 5-12 ...
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Command Phase Invalid Opcodes Execution Phase None. Index Pulse Gap 0 SYNC IAM IBM Format (MFM) C2* FC Toshiba Gap 0 SYNC IAM ...
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Result Phase LOCK 0 Bit 4 - Control Reset Effect (LOCK) Same as bit 7 of opcode in command phase. 5.7.7 The MODE Command This command selects the special features of the ...
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A software reset enables burst mode, i.e., clears this bit to its default value the LOCK bit (bit 7 of the op- code of the LOCK command BST retains its value ...
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Execution Phase Internal registers are written. Result Phase None. 5.7.8 The NSC Command The NSC command can be used to distinguish between the FDC versions and the 82077. Command Phase ...
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Execution Phase Internal registers are written. TABLE 5-15. Effect of Drive Mode and Data Rate on FORMAT TRACK and WRITE DATA Commands Data Rates Drive Mode 250, 300 or 500 Kbps Conventional Perpendicular Mbps Conventional Perpendicular TABLE ...
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Single track. The controller stops at the last sector of side 0. 1: Multiple tracks. the controller continues to side 1 af- ter reaching the last sector of side 0. Second Command Phase Byte Bits 1,0 - Logical Drive ...
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TABLE 5-17. Skip Control Effect on READ DATA Command Skip Control Data Sector Control Mark Bit 6 Type Read? (SK) of ST2 0 Normal Deleted Normal Deleted N 1 After finding ...
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TABLE 5-18. Result Phase Termination Values with No Error Multi-Track Head # End of Track (EOT) (MT) (HD) Sector Number 0 0 < EOT EOT 0 1 < EOT EOT 1 0 < EOT ...
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Execution Phase There is no data transfer during the execution phase of this command. An interrupt is generated when the execution phase is completed. The READ ID command does not perform an implied seek. After waiting the Delay Before Processing ...
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Head Number Sector Number Bytes-Per-Sector Code 5.7.14 The RECALIBRATE Command The RECALIBRATE command issues pulses that make the head of the selected drive step out until it reaches track 0. Command Phase ...
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Software should ensure that the RELATIVE SEEK com- mand is issued for only one drive at a time. This is because the drives are actually selected via the Digital Output Reg- ister (DOR), which can only select one drive at ...
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TABLE 5-21 "The Effect of Scan Commands on the ST2 Register" shows how all the scan commands affect bits 3,2 of the Status 2 (ST2) result phase register. See Section 5.5.3 "Result Phase Status Register 2 (ST2)" on page 108. ...
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The SENSE INTERRUPT Command The SENSE INTERRUPT command returns the cause of an interrupt that is caused by the change in status of any disk drive SENSE INTERRUPT command is issued when no inter- rupt is pending ...
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The SET TRACK Command This command is used to verify (read) or change (write) the number of the present track. This command could be useful for recovery from disk track- ing errors, where the true track number could be ...
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The parameters used by this command are undefined after power up, and are unaffected by any reset. Therefore, soft- ware should always issue a SPECIFY command as part of an initialization routine to initialize these parameters. Terminating this command does ...
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Bits 3-0 - Delay Before Processing Factor These bits specify a factor that is multiplied by a con- stant to determine the delay before command process- ing starts, i.e., from selection of a drive motor until a read or write ...
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Execution Phase Data is read from the disk, as the controller checks for valid address marks in the address and data fields. This command is identical to the READ DATA command, except that it does not transfer data during the ...
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If there is no match, the controller waits to find the next sec- tor address field. This process continues until the desired sector is found error condition occurs, the Interrupt Control (IC) bits (bits 7,6) in ST0 are ...
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... Result Phase Status Register 2 (ST2) Track Number Head Number Sector Number Bytes-Per-Sector Code DR0 DR1 PC87317 MTR0 www.national.com Upon terminating the execution phase of the WRITE DATA command, the controller asserts IRQ6, indicating the begin- ning of the result phase. The microprocessor must then 2 ...
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... PARALLEL PORT CONFIGURATION The PC87317VUL parallel port device offers a wide range of operational configurations. It utilizes the most advanced protocols in current use, while maintaining full backward compatability to support existing hardware and software. It ...
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In SPP Extended mode, parallel data transfer is bi-direc- tional. TABLE 6-12 "Parallel Port Pinout" on page 160 lists the output signals for the standard 25-pin, D-type connec- tor. Configuration Operation Mode Time SPP Compatible Configuration at SPP Extended System ...
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TABLE 6-4. SPP DTR Register Read and Write Modes Bit 5 of Mode RD WR CTR Data written to PD7-0. SPP Com- Data read from the out- patible Data written to ...
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Bit Status This bit reflects the current state of the printer paper end signal (PE). The printer sets this bit high when it detects the end of the paper. 0: Printer has paper. 1: End of paper ...
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Bits 7,6: Reserved These bits are reserved and are always 1. 6.3 ENHANCED PARALLEL PORT (EPP) MODES EPP modes allow greater throughput than SPP modes by supporting faster transfer times ( 32-bit data trans- fers in a single ...
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SPP or EPP Control Register (CTR) This control port is read or write. A write operation to it sets the state of four pins on the 25-pin D-shell connector, and controls both the parallel port interrupt enable and direction. ...
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EPP Data Register 3 (DATA3) This is the fourth EPP data register only accessed to transfer bits 24 through 32-bit read or write to EPP Data Register 0 (DATA0 ...
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EPP Data register, re- place the address strobe (ASTRB signal) and the EPP Ad- dress register, respectively. EPP Revision 1.7 and 1.9 Zero Wait State (ZWS) Ad- dress Write and Read Operations The following ...
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D7-0 RD WAIT ASTRB WRITE PD7-0 IOCHRDY ZWS FIGURE 6-16. EPP 1.9 Address Read EPP 1.9 Data Write and (Backward) Data Read This procedure writes to the selected peripheral drive or register. EPP 1.9 data read and write operations are ...
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EIR and EDR registers. See Section 6.5.2 "Second Level Offsets" on page 146. TABLE 6-6. Extended Capabilities Parallel Port (ECP) Registers Offset Symbol Description 000h DATAR Parallel Port Data Register 000h ...
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ECP Data Register (DATAR) The ECP Data Register (DATAR) register is the same as the DTR register (see Section 6.2.2 "SPP Data Register (DTR)" on page 138), except that a read always returns the values of the PD7-0 signals ...
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ECP Control Register (DCR) Reading this register returns the register content (not the signal values SPP mode Reset Required Data Strobe ...
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Bits 7-5 of ECR = 011 Reset Required Data Bits FIGURE 6-22. DFIFO Register Bitmap 6.5.9 ...
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Bits 1,0 - DMA Channel Select These bits reflect the value of bits 1,0 of the PP Config0 register (second level offset 05h). Microsoft’s ECP Pro- tocol and ISA Interface Standard defines these bits as shown in TABLE 6-7 "ECP ...
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The DMA and the above interrupts are not dis- abled. 1: The DMA and the above three interrupts are dis- abled. Bit 3 - ECP DMA Enable 0: The DMA request signal (DRQ3-0) is set to TRI- STATE and ...
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ECP Extended Data Register (EDR) This read/write register is the data port of the control regis- ter indicated by the index stored in the EIR. Reading or writ- ing this register reads or writes the data in the control ...
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Bits 2-0 - Reserved Bit 3 - EPP 1.7 ZWS Control Upon reset this bit is initialized to 0. This bit controls as- sertion of ZWS on EPP 1.7 access. There is no ZWS assertion on SPP and on EPP ...
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Actual ECP DMA routing is controlled by the DMA channel select register (index 74h) of this log- ical device. Microsoft’s ECP protocol and ISA interface standard de- fine bits 1 and 0 of CNFGB as shown in ...
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ECP Mode ECP Mode (ECR Bits) Name Standard Write cycles are under software control. STB, AFD, INIT and SLIN are open-drain output signals. Bit 5 of DCR is forced to 0 (forward direction) and ...
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When ACK is asserted the ECP drives AFD high. When AFD is high the peripheral device deasserts ACK. The ECP reads the PD7-0 byte, then drives AFD low. When AFD is low the peripheral device may change BUSY and PD7-0 ...
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PARALLEL PORT REGISTER BITMAPS 6.7.1 EPP Modes Reset Required Data Bits ...
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ECP Modes Bits 7-5 of ECR = 000 or 001 Reset Required Data Bits Bits ...
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Bits 7-5 of ECR = 111 Configuration Register Reset Required DMA Channel Select Reserved Interrupt Select IRQ Signal Value Reserved ...
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PARALLEL PORT PIN/SIGNAL LIST TABLE 6-12 "Parallel Port Pinout" shows the standard 25-pin, D-type connector definition for parallel port operations. Connector Pin ...
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Enhanced Serial Port with IR - UART2 (Logical Device 5) 7.0 Enhanced Serial Port with IR - UART2 (Logical Device 5) UART2 supports standard 16450/16550, Enhanced UART and InfraRed (IR) modes. This module provides advanced, versatile serial communi- cations features ...
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Enhanced Serial Port with IR - UART2 (Logical Device 5) BANK 6 BANK 5 BANK 4 BANK 3 BANK 2 BANK 1 BANK 0 Offset 07h Offset 06h Offset 05h Offset 04h LCR/BSR Offset 02h Offset 01h Offset 00h 16550 ...
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Enhanced Serial Port with IR - UART2 (Logical Device 5) Data transfer takes place by use of data buffers that inter- face internally in parallel and with the external data channel in a serial format. 16-byte data FIFOs may reduce ...
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Enhanced Serial Port with IR - UART2 (Logical Device value start bit, followed by eight data bits (LSB first), an optional parity bit, and ending with at least one stop bit with a binary value of 1. ...
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Enhanced Serial Port with IR - UART2 (Logical Device 5) the stream of samples can be used to reconstruct the in- coming bit string. To obtain good resolution, a fairly high sampling rate should be selected. The “Programmed-T-Period” mode should ...
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Enhanced Serial Port with IR - UART2 (Logical Device 5) Fallback can occur in any mode. In Extended UART mode, fallback is always enabled. In this case, when a fallback oc- curs, the following happens: Transmission and Reception FIFOs switch ...
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Enhanced Serial Port with IR - UART2 (Logical Device 5) TXD is accessed during CPU write cycles used to write data to the Transmitter Holding Register when the FIFOs are disabled the TX_FIFO when the FIFOs ...
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Enhanced Serial Port with IR - UART2 (Logical Device Disable Modem Status Interrupts (MS_EV) (De- fault). 1: Enable Modem Status Interrupts (MS_EV). Bits 7-4- Reserved These bits are reserved. Interrupt Enable Register (IER), in the Extended Modes ...
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Enhanced Serial Port with IR - UART2 (Logical Device 5) cles.The Event Identification Register (EIR) indicates the in- terrupt source. The function of this register changes according to the selected mode of operation. Event Identification Register (EIR), Non-Extended Mode When ...
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Enhanced Serial Port with IR - UART2 (Logical Device 5) Extended Mode, Read Cycles Reset Required RXHDL_EV TXLDL_EV LS_EV or TXHLT_EV MS_EV DMA_EV TXEMP-EV ...
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Enhanced Serial Port with IR - UART2 (Logical Device 5) TABLE 7-5. TX_FIFO Level Selection TXFTH (Bits 5,4) TX_FIF0 Threshold 00(Default Bits 7,6 - RX_FIFO Threshold Level (RXFTH1,0) These bits select the RX_FIFO interrupt threshold level. An ...
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Enhanced Serial Port with IR - UART2 (Logical Device parity is enabled, an even number of logic 1s are transmitted or checked. Bit 5 - Stick Parity (STKP) When Parity is enabled (PEN is 1), this bit, ...
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Enhanced Serial Port with IR - UART2 (Logical Device 5) Modem/Mode Control Register (MCR), Non-Extended Mode Non-Extended UART mode Reset Required ...
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Enhanced Serial Port with IR - UART2 (Logical Device 5) TABLE 7-10. The Module Operation Modes MDSL2 MDSL1 MDSL0 (Bit 7) (Bit 6) (Bit UART mode (Default ...
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Enhanced Serial Port with IR - UART2 (Logical Device cleared when a data character is written to the TXD register. Bit 6 - Transmitter Empty (TXEMP) This bit is set to 1 when the Transmitter Holding Regis- ...
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Enhanced Serial Port with IR - UART2 (Logical Device 5) Non-Extended Modes Reset Required Scratch Data FIGURE 7-17. SPR Register Bitmap 7.11.11 Auxiliary Status and Control Register (ASCR) This register shares a ...
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Enhanced Serial Port with IR - UART2 (Logical Device 5) In addition, a fallback mechanism maintains this compatibil- ity by forcing the UART to revert to 16550 mode if 16550 software addresses the module after a different mode was set. ...
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Enhanced Serial Port with IR - UART2 (Logical Device 5) 7.13.1 Baud Generator Divisor Ports, LSB (BGD(L)) and MSB (BGD(H)) These ports perform the same function as the Legacy Baud Divisor Ports in Bank 1 and are accessed identically, but ...
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Enhanced Serial Port with IR - UART2 (Logical Device 5) 7.13.2 Extended Control Register 1 (EXCR1) Use this register to control module operation in the Extend- ed mode. Upon reset all bits are set to 0. Extended Control and 7 ...
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Enhanced Serial Port with IR - UART2 (Logical Device 5) Bit 5 - Enable Transmitter During Loopback (ETDLBK) When this bit is set to 1, the transmitter serial output is enabled and functions normally when loopback is en- abled. Bit ...
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Enhanced Serial Port with IR - UART2 (Logical Device 5) 7.13.7 RX_FIFO Current Level Register (RXFLV) This read-only register returns the number of bytes in the RX_FIFO. It can be used for software debugging. Extended Modes ...
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Enhanced Serial Port with IR - UART2 (Logical Device 5) 7.14.3 Shadow of FIFO Control Register (SH_FCR) This read-only register returns the contents of the FCR reg- ister in bank FIFO ...
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Enhanced Serial Port with IR - UART2 (Logical Device 5) 7.16 BANK 5 – INFRARED CONTROL REGISTERS TABLE 7-20. Bank 5 Registers Register Offset Description Name 00-02h Reserved 03h LCR/ Link Control Register/ BSR Bank Select Register 04h IRCR2 Infrared ...
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Enhanced Serial Port with IR - UART2 (Logical Device 5) Bit 6 - Sharp-IR Modulation Disable (SHMD_DS) 0: Enables internal 500 KHz transmitter modulation. (Default) 1: Disables internal modulation. Bit 7 - Sharp-IR Demodulation Disable (SHDM_DS) 0: Enables internal 500 ...
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Enhanced Serial Port with IR - UART2 (Logical Device 5) Demodulation Control Reset Required DFR0 DFR1 DFR2 DFR3 DFR4 DBW0 DBW1 DBW2 FIGURE 7-35. ...
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Enhanced Serial Port with IR - UART2 (Logical Device 5) TABLE 7-25. Consumer-IR, Low Speed Demodulator (RXHSC = 0) (Frequency Ranges in KHz) DFR Bits min/max min max min 0 ...
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Enhanced Serial Port with IR - UART2 (Logical Device 5) DFR Bits min/max min 51. max 57.36 min 54. max 60.10 TABLE ...
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Enhanced Serial Port with IR - UART2 (Logical Device 5) TABLE 7-28. Transmitter Modulation Mode Selection RCCFG Bits Modulation Mode C_PLS Modulation mode. Pulses are generated continuously for the entire logic 0 bit time ...
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Enhanced Serial Port with IR - UART2 (Logical Device 5) — If AMCFG (bit 7 of IRCFG4) is set to 1, these bits drive the ID/IRSL(2-1) pins when Sharp-IR mode is selected. — If AMCFG is 0, these bits will ...
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Enhanced Serial Port with IR - UART2 (Logical Device 5) 0: Pin’s direction is input. 1: Pin’s direction is output. Bit 6 - Reserved Read/write 0. Bit 7 - Automatic Module Configuration (AMCFG) When set to 1, this bit enables ...
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Enhanced Serial Port with IR - UART2 (Logical Device Reset Required WLS0 WLS1 STB PEN EPS STKP SBRK BKSE ...
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Enhanced Serial Port with IR - UART2 (Logical Device 5) Legacy Baud Generator Divisor Reset Required Least Significant Byte of Baud Generator Legacy Baud Generator Divisor ...
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Enhanced Serial Port with IR - UART2 (Logical Device Module Revision Reset Required Revision ID(RID 3-0) Module ID(MID 7- ...
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Enhanced Serial Port with IR - UART2 (Logical Device Reset Required MCFR(4-0) MCPW(2-0) Consumer-IR Mode ...
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Enhanced Serial Port - UART1 (Logical Device 6) 8.0 Enhanced Serial Port - UART1 (Logical Device 6) UART1 supports serial data communications with a remote peripheral device or modem using a wired interface. The module can function as a standard ...
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Enhanced Serial Port - UART1 (Logical Device 6) 8.2.1 16450 or 16550 UART Mode The module defaults to 16450 mode after power up or reset. UART 16550 mode is equivalent to 16450 mode, with the addition of a 16-byte data ...
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Enhanced Serial Port - UART1 (Logical Device 6) More than 64 sec or four character times, whichever is greater, have elapsed since the last byte was read from the RX_FIFO by the CPU. 8.4 AUTOMATIC FALLBACK TO A NON-EXTENDED UART ...
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Enhanced Serial Port - UART1 (Logical Device 6) TXD is accessed during CPU write cycles used to write data to the Transmitter Holding Register when the FIFOs are disabled the TX_FIFO when the FIFOs are en- ...
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Enhanced Serial Port - UART1 (Logical Device 6) Interrupt Enable Register (IER), in the Extended Mode Figure 8-6 shows the bitmap of the Interrupt Enable Regis- ter in these mode. IER in Extended Mode ...
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Enhanced Serial Port - UART1 (Logical Device 6) TABLE 8-3. Non-Extended Mode Interrupt Priorities EIR Bits Priority Interrupt Type Level None Highest Line Status ...