PC87570 National Semiconductor, PC87570 Datasheet
PC87570
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PC87570 Summary of contents
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... Interface, two Multi-Function 16-Bit Timers (MFT16), periodic interrupt timer and WATCHDOG and DAC. The PC87570 highly efficient architecture and its on-chip peripherals, supporting functions and low power consump- tion, provide a highly integrated solution for portable note- book PCs, sub-notebook PCs and other portable devices. ...
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Features • CR16A Core — 16-bit embedded RISC processor core • Bus Interface Unit (BIU) — Three address zones for static devices (SRAM, ROM FLASH, I/O) — Configurable wait states and fast read bus cycles • Internal Memory — 2048 ...
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... Generates the System Management Interrupt (SMI) • 160-pin PQFP and 176-pin TQFP packages External Mouse Interface Interface 32KX1/32KCLKIN 32KX2 V BAT HD7-0 HA18-0 HAEN HIOR HIOW HIOCHRDY HMEMRD HMEMWR PC87570 HMEMCS IRQ1 IRQ8 IRQ11 IRQ12 EXINT0,10,11,15 GA20 HRSTO HPWRON HMR ENV1 ENV0 SHBM HRMS HDEN TRIS 3 ...
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Highlights ....................................................................................................................................................... 1 Introduction 1.0 1.1 INTERNAL ARCHITECTURE .................................................................................................... 14 1.1.1 Processing Unit ........................................................................................................... 14 1.1.2 BIU ............................................................................................................................... 14 1.1.3 Memory ........................................................................................................................ 14 1.1.4 HBI ............................................................................................................................... 14 1.1.5 Peripherals .................................................................................................................. 14 1.2 EXPANSION OPTIONS ............................................................................................................. 15 1.3 OPERATING ENVIRONMENTS ................................................................................................ ...
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... USAGE HINTS .......................................................................................................................... 49 5.4.1 Shared Memory ........................................................................................................... 49 5.4.2 Wake-Up from Host ..................................................................................................... 50 5.4.3 Host Power-on Indication ............................................................................................ 50 5.5 HOST ACCESS TO PC87570 RESIDENT I/O DEVICES ......................................................... 50 5.5.1 Host Access to Configuration Registers ...................................................................... 50 5.5.2 Host Access to Resident I/O Devices .......................................................................... 50 5.5.3 Host Bus I/O Cycles .................................................................................................... 50 5.6 KBC CHANNEL ......................................................................................................................... 50 5.6.1 Status Register ...
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... SYSTEM CONSIDERATIONS ................................................................................................... 53 5.11.1 Reset Configuration ..................................................................................................... 53 5.11.2 Host Power-On (HPWRON) Indication Input ............................................................... 53 5.11.3 Host Master Reset (HMR) Input .................................................................................. 53 5.11.4 Host Reset Output (HRSTO) from PC87570 ............................................................... 53 5.11.5 HDEN Strap ................................................................................................................. 54 5.11.6 GA20 Pin Functionality ................................................................................................ 54 5.11.7 Host Driven Wake-Up .................................................................................................. 54 5.11.8 APC-ON and APC-OFF Events ................................................................................... 54 5 ...
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IRQ Enable Register (IRQE) ....................................................................................... 63 Real-Time Clock (RTC) and Advanced Power Control (APC) 6.0 6.1 FEATURES ................................................................................................................................ 64 6.2 RTC FUNCTIONAL DESCRIPTION .......................................................................................... 64 6.2.1 Host Bus Interface ....................................................................................................... 64 6.2.2 Core Bus Interface ....................................................................................................... 64 6.2.3 Bank ...
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FUNCTIONAL DESCRIPTION .................................................................................................. 76 7.2.1 Setting Clock Frequency ............................................................................................. 76 7.2.2 Fast Clock Setting ....................................................................................................... 77 7.3 HFCG REGISTERS ................................................................................................................... 77 7.3.1 HFCG Control Register (HFCGCTRL) ........................................................................ 77 7.3.2 HFCGM Low Value Register (HFCGML) ..................................................................... 77 7.3.3 HFCGM High ...
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FUNCTIONAL DESCRIPTION .................................................................................................. 84 10.2.1 Trigger Conditions ....................................................................................................... 86 10.2.2 Pending Flags .............................................................................................................. 86 10.2.3 Input Enable ................................................................................................................ 86 10.2.4 Interrupts ..................................................................................................................... 86 10.2.5 Input Assignments ....................................................................................................... 86 10.3 MIWU REGISTERS ................................................................................................................... 86 10.3.1 Edge Detection Register 1(WKEDG1) ......................................................................... ...
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General PS/2 Interface Operation ............................................................................... 91 12.3.4 Transmit Mode ............................................................................................................. 93 12.4 SHIFT MECHANISM DISABLED ............................................................................................... 94 12.4.1 Clock Signal Control .................................................................................................... 94 12.4.2 Data Signal Control ..................................................................................................... 94 12.4.3 Interrupt Generation .................................................................................................... 94 12.5 PS/2 INTERFACE REGISTERS ................................................................................................ ...
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Slow Speed Clock ..................................................................................................... 107 14.3.5 Counter Clock Source Select .................................................................................... 108 14.4 TIMER/COUNTER AND ACTION UNIT .................................................................................. 108 14.4.1 Operation Modes ....................................................................................................... 108 14.4.2 Timer Interrupts ......................................................................................................... 113 14.4.3 Timer I/O Functions ................................................................................................... 113 14.5 MFT16 REGISTERS ................................................................................................................ ...
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Sampling Time ........................................................................................................... 121 16.2.9 Polling Driven Operation ............................................................................................ 121 16.2.10 Interrupt Driven Operation ......................................................................................... 121 16.2.11 Overflow .................................................................................................................... 121 16.3 OPERATION MODES ............................................................................................................. 122 16.4 ADC REGISTERS ................................................................................................................... 123 16.4.1 ADC Status Register (ADCST) .................................................................................. 123 16.4.2 ADC ...
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MONITORING ACTIVITY DURING DEVELOPMENT ............................................................. 130 18.4.1 The Bus Status Signals ............................................................................................. 130 18.4.2 Transaction Effects on the External Bus ................................................................... 130 18.4.3 Pipe Status Signals ................................................................................................... 131 18.5 DEVELOPMENT SYSTEM REGISTERS ................................................................................ 131 18.5.1 Debug Configuration Register (DBGCFG) ...
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... PC87570 can generate interrupt requests to the host processor via IRQ1, IRQ12, IRQ11 and IRQ8 for the Keyboard, Mouse, PM and RTC/APC handlers, respective- ly. This allows the PC87570 to be used with polling or inter- rupt driven schemes. The PC87570 communicates with a host processor over an ISA compatible, host interface bus ...
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... Base Memory (the IRE environment) is identi- cal to that in off-chip Base Memory (IRD and DEV environ- ments); i.e., the operation is cycle-by-cycle compatible. PC87570 devices are tested to ensure that they operate in either IRE or IRD environment. Only selected parts are test- ed for operation in DEV environment. ...
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... IRE Environment In this environment, after reset, (internal power-on reset cir- cuit or an external pulse on HMR pin), the PC87570 starts running the code written in the internal mask-ROM. This ROM contains the PC87570’s boot program which is read- only. The boot-code size can Kbytes. After com- pletion of the boot program, the process is handed over to the External Memory ...
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... Figure 1-2 illustrates a system in IRD environment. External Mouse Auxiliary PS/2 Interface Interface SEL1 RD WR1-0 SEL0 A18-16, A15-0 D15-8 D7-0 SELIO KBSOUT15-0 KBSIN7-0 PA6-0 PB7-0 PC87570 PC7-0 PD7-0 PE1-0 PF7-0 PG4-0 PH5-0 EXINT0,10,11,15 PFAIL RING SWIN TA TB SCL SDA AD7-0 V REF ...
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... Figure 1-3 shows a system in DEV environment. External Mouse Auxiliary PS/2 Interface Interface SEL1 RD WR1-0 SEL0 A18-16, A15-0 D15-8 D7-0 SELIO KBSOUT15-0 KBSIN7-0 PA6-0 PB7-0 PC87570 PC7-0 PD7-0 PE1-0 PF7-0 PG4-0 PH5-0 EXINT0,10,11,15 PFAIL RING SWIN TA TB SCL SDA AD7-0 V REF ...
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... HA3 HA4 HA5 HA6 HA7 160 HA8 1 5 Signal/Pin Connection and Description 110 105 100 95 PC87570 160-pin PQFP 160-pin PQFP Package Order Number PC87570-ICC/VUL NS Package Number VUL160 PD5/AD5 PD4/AD4 PD3/AD3 PD2/AD2 PD1/AD1 75 PD0/AD0 V REF PFAIL PB7/SWIN HRSTO(PB6) 70 PB5(GA20) PB4/TB/EXINT10 PB3/TA ...
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... HA5 HA6 HA7 HA8 175 www.national.com Signal/Pin Connection and Description 120 115 110 105 PC87570 176-pin TQFP 176-pin Thin Quad Flatpack (TQFP) Order Number PC87570-ICC/VPC NS Package Number VPC176 20 100 PD5/AD5 85 PD4/AD4 PD3/AD3 PD2/AD2 PD1/AD1 PD0/AD0 80 V REF PFAIL PB7/SWIN HRSTO(PB6) PB5(GA20) 75 ...
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... SIGNAL/PIN DESCRIPTIONS Refer to Table 2-2 for an alphabetical listing of all PC87570 signals and pins, as well as brief descriptions. The following abbreviations are used in the Type column in this table. Symbol Description TTL Input, TTL compatible CMOSS Input, CMOS with Schmidt Trigger STRAP Input with Schmidt characteristics and an internal ...
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... Refer to Section 19.5.4 on page 150. Host Data. Bi-directional data bus used to inter- face the PC87570 to the peripheral data bus of the host. Refer to Section 19.5.4 on page 150. Host Device Enable, strap pin. When pulled high during power-up reset, con- fi ...
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... See also Table 2-5 on page 27. For AC parameters, refer to Section 19.5.4 on page 150. CMOSS - Master Reset. A rising edge that resets the PC87570. See details at Section 2.3.4 on page 26. CMOSS - Host Power On. Indicates that the host power supply is on, and the host bus interface signals are valid ...
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Pin Number Signal 160-pin 176-pin KBSIN7-0 27-34 29-36 KBSOUT15-0 35-50 37-42, 47-56 PA6-0 121, 120, 135, 130 11, 10, 149, 148, 163, 162, 143, PB7-0 72-65 78-71 PC2-0 57-55 63-61 PC7-3 64-62, 59, 58 70-68, 65, 64 TTL-PU ...
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... Buffer Type Input Output TTL - Timer pin B STRAP - TRI-STATE strap option. When high, during power-up reset, causes the PC87570 to float all its output and I/O signals Battery supply. This is the 2.4 - 5.5V battery ULR voltage for the RTC circuitry. N/A N/A Digital ...
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... The reset continues for a period of about 16 clock cycles after the HMR rising edge. See details at Figure 19-26 on page 154. The PC87570 can operate when HMR is still active (high). In this case, the host bus I/F is inactive. Note: In all PC87570 revisions, before C3, the HMR (for- merly HMR) input pin is ignored when HPWRON is 0, dis- abling reset execution ...
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... Strap Inputs During Idle Mode When the PC87570 is in Idle mode and shared memory with host BIOS is enabled, the A(16-18) signals are forced to the value sampled on the strap input that shares the pin. This is done to reduce leakage currents on external resistors con- nected to that pin ...
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Pin Name PB0/RING PB1/SCL PB2/SDA PB3/TA PB4/TB/EXINT10 PB5/GA20 PB6/HRSTO PB7/SWIN PC0 PC1 PC2 PC3/EXINT0 PC4/EXINT11 PC5/EXINT15 PC6/PSCLK3 PC7/PSDAT3 PD0/AD0 PD1/AD1 PD2/AD2 PD3/AD3 PD4/AD4 PD5/AD5 PD6/AD6 PD7/AD7 PE0/HA18 PE1/A18 PF0/D8 PF1/D9 PF2/D10 PF3/D11 PF4/D12 PF5/D13 PF6/D14 PF7/D15 www.national.com Signal/Pin Connection and ...
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... PH3/PFS PH4/PLI PH5/ISE 1. PB5 is initialized upon reset as an output port with data set to 1. This allows the PC87570 firmware to use it as GA20. 2. PB6 is always configured as output and with its alternate function enabled. See Section 5.11.4 on page 53. 2.6 SYSTEM CONFIGURATION REGISTERS 2 ...
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... Either Flash EPROM or ROM devices may be used. The memory can 512 KByte. The PC87570 is mapped into a block of 56 KByte in the memory device. It may use all the block or part of it. The host can access any of the bytes in the Flash device. ...
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... AEN IOWR IORD ROMOE MEMWR ROMCS Figure 2-1. Sharing PC87570 Program Memory and BIOS Flash Memory 2.8.1 Accessing Base Memory Base Memory Configuration The environment setting controls the use of on-chip Base Memory (ROM), or off-chip Base Memory. In all cases, the memory access parameters (i.e., the number of wait and hold cycles) are as defined for zone1 of the BIU ...
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... Figure 2-2. On-Chip Base Memory (Zone 1) Address Range 256 K 192 K 128 PC87570 Address Map Figure 2-3. Off-Chip Base Memory (Zone 1) Address Range 2.8.2 Accessing External Memory External Memory Configuration is enabled whenever the Base Memory Shadow is off (MCFG.SHOFF=1). The BIU Zone 0 Configuration Register (SZCFG0) controls the memory access parameters ...
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... K 192 K 128 PC87570 Address Map Figure 2-4. External Memory (Zone 0) Address Range Table 2-7. External Memory Configuration Settings External MCFG Memory SHOFF Configuration Disabled 0 32K x8 1 64K x8 1 32K x16 1 64K x16 1 Table 2-8. External Memory Address Expansion Scheme SHBM PEALT ...
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Bus Interface Unit (BIU) The BIU directly interfaces with a wide variety of devices, in- cluding ROM, SRAM and FLASH memory devices and I/O devices. It interfaces via address, data and control buses, without the need for external glue ...
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When more than one T idle as a pause, the T cycles overlap and only one T idle is added. T clock cycles can be inserted between two consecutive idle accesses ...
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Early Write Bus Cycle If the BCFG.EWR configuration bit is 1, the BIU uses early write bus cycles; this allows removal of the RD signal from the memory device interface. The basic early write bus cy- cle takes three ...
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Bus Interface Unit (BIU) Normal Read CLK A0-18 SELx (x y) SELy (y x) D0- WR0-1 BST0-2 Figure 3-2. Early Write following Normal Read with 0 Wait T1 TIW T2 CLK A0-18 SELn D0-15 RD ...
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Late Write Bus Cycle If the BCFG.EWR configuration bit is 0, the BIU uses the late write bus cycle. The basic late write bus cycle takes two clock cycles. This write bus cycle requires the RD signal in the ...
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Bus Interface Unit (BIU Bus State Normal Read CLK A0-18 SEL0-1, SELIO D0-15 RD WR0-1 BST0-2 Figure 3-5. Late Write Bus Cycle Between Normal Read Bus Cycles with 0 Wait Bus State T1 CLK A0-18 SELn D0-15 RD ...
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Normal Read Bus Cycle A read bus cycle starts at T1, when the address is placed on the address bus, and SELn (or SELIO) is activated. WR0-1 are inactive, indicating that this is a read bus cycle. The RD ...
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SZCFGn.WAIT 0 Internal waits corresponding to SZCFGn.WAIT TIW RD: active Internal waits completed SZCFGn.{BW,WBR,BRE} = 001 Core attempts to read a word SZCFGn. SZCFGn.(WBR,BRE Core attempts to read a word Next address on A0-15, End of ...
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Bus State CLK A0-18 SELn D0-7 RD WR0-1 BST0-2 Figure 3-10. Normal Read Bus Cycle with 0 Wait on Burst T1 CLK A0-18 SELn D0-7 RD WR0-1 BST0-2 Figure 3-11. Normal Read Bus Cycle with 2 Internal Waits and 1 ...
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T Idle CLK A0-18 SELx (x y) SELy (y x) D0-15 RD WR0-1 BST0-2 3.3.7 I/O Expansion Bus Cycles The I/O expansion bus cycles enables you to implement the functionality of on-chip I/O ports (when the pins of the on- ...
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... Figure 3-14 shows an example of how two ports can be im- plemented off-chip, using I/O expansion. This example im- SELIO PC87570 Figure 3-14. Example of an Implementation of Two Ports Using I/O Expansion 1. This routing is for late write. If early write, SELIO is routed to CP and WR0 to CE. All other routing is unchanged. ...
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BIU REGISTERS 3.5.1 BIU Configuration Register (BCFG) The BCFG Register is a byte-wide, read/write register that controls the configuration of common features to all zones. On reset, BCFG is initialized to 07h Reserved Bit 0 - Early ...
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... USAGE HINTS The following usage hints will help you configure the BIU to max- imize PC87570 performance while avoiding contention on the data bus IRE environment, the access time to the internal ROM can use zero wait and zero hold cycles, but not fast reads ...
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... RAM array. Each system RAM read or write operation is one cycle long, and does not include any wait states. 4.2 INTERNAL ROM In IRE environment, the PC87570 provides 2 Kbytes of in- ternal ROM bits wide and can be accessed by byte or word transactions. In IRE environment, internal ROM is used as the system’s Base Memory ...
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... The HBI allows the host and CR16A core to share the same Flash memory. In this way, only one memory device is needed for both the host system BIOS, and for the PC87570 code. Memories other than Flash may be used. Both the host and the CR16A can access the three legacy I/O devices: ...
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... The PC87570 firmware can access the RTC only while the PC87570 is in Active mode so, it should use the fol- lowing sequence: 1. After arbitrating the use of the RTC with the host, set LKRTCHA ...
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... When an access to a device address is identified and the device is enabled, an internal chip select signal is generated. In addition to the chip select signal, the PC87570 uses HA0 to distinguish between the two RTC/APC registers, and HA2 to distinguish between the two registers of the KBC and PM ports ...
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... DBBOUT. DB- BOUT should be written by the firmware running on the CR16A only when this bit is cleared. The PC87570 supports polling and interrupt communication schemes with the host. Both keyboard interrupt (IRQ1) and mouse interrupt (IRQ12) schemes are supported. ...
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... OBF in the HIKMST Register. In normal polarity mode (IRQNPOL in the HIIRQC Register is 0), the PC87570 supports two types of interrupts: edge or level. When an edge interrupt is selected (IRQM in the HI- IRQC Register is not 0), the interrupt signal default value is high (1). When an interrupt signal needs to be sent (i.e., the corresponding OBF flag is set), a negative pulse is generat- ed ...
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... Host Master Reset (HMR) Input The PC87570 is reset by an internal reset signal generated on the rising edge of its power supply. The chip is also reset on the rising edge of the HMR pin. See more details in Sec- tion 2.3.4. 5.11.4 Host Reset Output (HRSTO) from PC87570 HRSTO is one of the sources for host soft reset commands (i ...
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... Host Driven Wake-Up When the PC87570 is in Idle mode, it will wake-up to Active mode in response to an access on the host interface bus. A wake-up event is sent to the MIWU (WUI26) in any of the ...
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... Res Bit 0 - Host Reset Out (HRSTO) Enables the PC87570 to generate a host soft reset via firmware, using the HRSTO pin. The pin is held low (re- set is active) for as long this bit 1. Se also Figure 5-5 on page 54 0: De-asserts (high) the HRSTO signal (unless reset is extended via its other sources) ...
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... RTC Data Register. A read from this bit reads the RTC Data Register. This register should be accessed by the PC87570 firmware, only when LKRTCHA in the CST1 Register is set. This register actually access the Data Register located at host default address 0071h ...
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... The HIKMST Register is a byte wide, read/write register. It provides the status of the host interface keyboard channel buffers (DBBIN and DBBOUT) and a means for the PC87570 to send status bits to the host. This register can also be read by a host read operation from address 64h. HIKMST is cleared (00h) on reset. ...
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... The HIPMST Register is a byte wide, read/write register. It provides the status of the host interface PM channel buffer registers (DBBIN and DBBOUT) and a means for the PC87570 to send data to the host status bits. This register is read by a host read operation from address 66h. HIPMST is cleared (00h) on reset. ...
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... B5, DA, ED, F6, FB, 7D, BE, DF, 6F, 37, 1B, 0D, 86, C3, 61, B0, 58, 2C, 16, 8B, 45, A2, D1, E8, 74, 3A, 9D, CE, E7, 00, 00. If the sequence is successfully completed, the PC87570 enables the configuration base address update. If any of the write operations in this sequence do not match, the enable process is stopped and the hardware resets the LFSR Register to its initial value (step 1) ...
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... Software can now access the configuration Index and Data Registers, for setting the PC87570 interface according to the system configura- tion. Once the initial setting of the configuration registers is suc- cessfully completed, it cannot be set again until reset is ap- plied ...
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... MSB ID Value 5.14.2 Identification Type Register (SIDT) The SIDT Register identifies the chip type. Its value is fixed as 01h for the PC87570. This register is a read only register. Data written ignored MSB ID Value Host Bus Interface (HBI) 5.14.3 Identification Revision Register (SIDR) The SIDR Register identifies the chip revision ...
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... Function Enable Register (FER) The FER Register enables and disables the host interface to various functions in the PC87570. On reset, the host may change the contents of the bits in this register. Bits in FER may be write protected (locked) by setting the corresponding bit in the FLR Register ...
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A read or write access by the host to the address specified by KBCCSAH, KBCCAL generates a chip select to the KBC channel (HKBCCS). Bit Enable (PME channel cannot be accessed by the host; ...
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... PC87570 firmware. Through these two registers, the core can access all the RTC registers and the CMOS RAM. Ded- icated hardware prevents conflict when both the host and the PC87570 firmware access the RTC. For more details, see CR16A Core Access to RTC in Section 5.3 on page 49. 6.2.3 ...
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Real-Time Clock (RTC) and Advanced Power Control (APC) 6.2.6 Internal Oscillator The internal oscillator employs an external crystal connect the on-chip amplifier. The on-chip amplifier is accessi- ble on the 32KX1 input pin and 32KX2 output pin. See ...
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Real-Time Clock (RTC) and Advanced Power Control (APC) Divider Chain Reset DV2 DV1 DV0 CRA Register 32.768 KHz To other modules 32KX1 32KX2 Figure 6-3. Divider Chain Control Bits ...
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... Power Supply The PC87570 is supplied from two supply voltages, as shown in Figure 6-4: System standby power supply voltage, V Backup voltage, from low capacity Lithium battery. ...
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Real-Time Clock (RTC) and Advanced Power Control (APC) 6.2.13 System Bus Lockout During power-up or power-down, spurious bus transactions from the host may occur. To protect the RTC internal regis- ters from corruption, all inputs are automatically locked out. The ...
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Real-Time Clock (RTC) and Advanced Power Control (APC) The upper 64 bytes of bank addresses are utilized as fol- lows: Bank 0 supplies an additional 64 bytes of memory- backed RAM. Bank 1 uses the upper 64 bytes for functions ...
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Real-Time Clock (RTC) and Advanced Power Control (APC) Table 6-4. Divider Chain Control and Bank Selection DV2 DV1 DV0 Selected CRA CRA CRA Bank Bank 0 Oscillator Disabled Bank 0 Oscillator ...
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Real-Time Clock (RTC) and Advanced Power Control (APC) Bit 7 - Interrupt Request Flag (IRQF) This read-only bit mirrors the value on the IRQ8 output signal. When IRQ8 is active (low), IRQF is 1. The IRQ pin is put in ...
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... Real-Time Clock (RTC) and Advanced Power Control (APC) Power On This is the normal state when the PC87570 is powered on. This state may be initiated by various events in addition to physically switching the system on. The PC system and the PC87570 device are powered by V CC. Note: The APC does not function when the 32.768 KHz oscillator is not running ...
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Real-Time Clock (RTC) and Advanced Power Control (APC) 6.6.1 APC Control Register 1 (APCR1 Res SOC Bits 4-0 - Reserved Bit 5 - Software Off Command (SOC) This bit is write-only and non-sticky. Read returns ...
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Real-Time Clock (RTC) and Advanced Power Control (APC) 6.7 REGISTER BANKS Format Offset Register BCD 00h Seconds 00-59 01h Seconds 00-59 Alarm 02h Minutes 00-59 03h Minutes Alarm 00-59 04h Hours 12H 01-12 (AM) 81-92 (PM) 24H 00-23 05h Hours ...
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Real-Time Clock (RTC) and Advanced Power Control (APC) Format Offset Register BCD 00h- 3Fh 40h- 47h 48h Century 00-99 49h- 4Fh 50h Upper RAM Address Port 51h- 52h 53h Upper RAM Data Port 54h- 7Fh Format Offset Register BCD 00h ...
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... The HFCG is designed to be tightly coupled with the PMC. The HFCG Enable signal coming from the PMC is input to the HFCG, enabling or disabling clock generation in Idle mode. The PMC enables the CLK for the PC87570 in Active mode. Figure 7-1 shows the HFCG blocks, and the operating en- vironment ...
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Fast Clock Setting The HFCG maintains an internal 14-bit HFCGI variable. The HFCGI variable is defined by two byte-wide registers: HFCGIL and HFCGIH. If new HFCGM and HFCGN values are loaded, the frequency multiplier automatically searches for the HFCGI ...
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HFCGI Low Value Register (HFCGIL) The HFCGIL Register is a byte-wide, read/write register con- taining the lower eight bits of the frequency multiplier HFCGI value. Data written to the register is stored in the setup buffer. Reading the register ...
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... After reset, the PC87570 is in Active mode. Idle Mode In Idle mode, the clock is stopped for most of the PC87570. Only the PMC and a limited number of other modules con- tinue to operate at the 32.768 KHz clock rate; they can wake-up the PC87570 and resume instruction execution when required ...
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... The PMCR Register is a byte-wide, read/write register that enables you to switch from Active to Idle mode. In addition, it controls the operation of the HFCG in Idle mode by en- abling or disabling it. The PC87570 enters Idle mode after execution of a WAIT instruction. The PMCR Register must be set before executing the WAIT instruction. ...
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... External Interrupt Inputs The external interrupt inputs are asynchronous. They are recognized by the PC87570 during clock cycles in which the input setup and hold time requirements are satisfied. To use an external interrupt that is shared with an I/O port, config- ure the I/O port to its alternate function (see Table 2-5 on page 27) ...
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... Bit 0 -PFAIL Trap Enable (EN) An NMI trap is generated when the EN bit is set, and the PFAIL pin changes its value from high to low. The bit is cleared by hardware on reset, and whenever the trap occurs. The EN bit can be set and cleared by PC87570’s firmware. 82 Priority Lowest 3 ...
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Bit 1 - PFAIL Pin Value (PIN) Holds the current (non-inverted) PFAIL pin value. PIN is a read only bit; data written ignored. 9.3.3 Interrupt Vector Register (IVCT) The IVCT Register is a byte-wide, read only register. ...
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... APC output pulse. 3. The ICU is provided with the OR of WKINTA and WKO24 as the interrupt input. 4. The wake-up input is triggered when the host accesses the PC87570. See Sec- tion 5.11.7 on page 54. Configure the WUI26 for falling edge detection. 5. This input does not generate an interrupt. ...
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WUI10 WUI17 WKEDG2 WUI20 WUI27 WKEDG2 WUI30 WUI37 WKEDG3 www.national.com Multi-Input Wake-Up (MIWU) Peripheral Bus ....................... 7 0 WKEN1 WKPND2 1 SEL 0 SEL 1 0 ....................... 7 0 WKEN2 WKPND2 1 ...
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The MIWU is active while in Idle state. In this state, all clocks of the device are stopped. Therefore the detection of a trigger condition on an input, and the resulting set of the pending flag, are not synchronous to ...
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Pending Register 3 (WKPND3) The WKPND3 Register is a byte-wide, read/write register, that latches the occurrence of a selected trigger condition associated with the input signals WUI30 to WUI37. For a detailed description of the register see the above ...
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... General Purpose I/O (GPIO) Ports The PC87570 provides GPIO pins. Some GPIO signals share their pins with an alternate function (see Sec- tion 2.5 on page 27). 11.1 FEATURES The GPIO ports are subdivided into the following groups, each with its own unique set of features: ...
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GPIO PORT REGISTERS 11.3.1 Port Alternate Function Register (PxALT) The PxALT Register is a byte-wide, read/write register. It de- termines if the port will be used as a GPIO port or in its alter- nate function. When cleared (0), ...
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... PS/2 data reduces code overhead and performance requirements from the CompactRISC CR16A core, and improves the overall interrupt latency of the PC87570. The shift mechanism includes an 8-bit shift reg- ister, a state machine and control logic that handle both in- coming and outgoing data. ...
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... It should be programmed to identify a low level on the clock or data lines of the enabled channels. In this con- figuration, a start bit causes the PC87570 to switch from Idle mode to Active mode. Once Active mode is reached, the firmware should cancel the transaction just started and then enable a re-transmission of the information by the device ...
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... PSTAT.PERR is set stop bit was detected low instead of high, the PSTAT.RFERR bit is set. Input Signals Debounce The PC87570 performs a debounce operation on the clock input signal before determining its logic value. PSCON.IDB determines for how many clock cycles the input signal must be stable to define a change in its value ...
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... When a PS/2 device senses the clock signal high with the data signal low, it identifies a transmit request from the PC87570. The two channels not in use are disabled by forcing “0” on their clock lines. ...
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I/O Inhibit CLK DATA Start Bit Figure 12-6. PS/2 Transmit Data Byte Timing When a start bit is detected, data transmission begins by outputting bit-0 (LSB) of the transmitted data and setting the data bits WDAT1, WDAT2 and WDAT3 in ...
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... Bits 6-4 - Input Debounce (IDB) This IDB field defines the number of PC87570 clock cy- cles during which the clock input is expected to be sta- ble before the shift mechanism identifies its new value. This protects the shift mechanism from false edge de- tections ...
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... WDAT1 bit to force the transmit sig- naling (low) to the PS/2 device. WDAT1 is set by the hardware after the PC87570 de- tected a start bit (i.e., on entering the Transmit Active state transmission is aborted before the transmit- active state, WDAT1 should be set (1) prior to disabling the channel ...
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Bit 0 - Start of Transaction Interrupt Enable (SOTIE) This bit is used for enabling the interrupt generation on a transaction start detection. When set (1), the interrupt signal (PSINT1) to the ICU is active (1) whenever the PSTAT.SOT bit ...
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ACCESS.bus (ACB) Interface The ACB interface is a two wire serial interface compatible with the ACCESS.bus physical layer also compatible 2 with Intel’s SMBus and Philips’ bus. The module can be configured as a bus ...
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SDA line during the acknowledge clock pulse, thus signalling the correct reception of the last data byte, and its readiness to receive the next byte. Figure 13-4 illus- SDA MSB SCL S Start Condition SDA SCL S Start ...
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... Sending the Address Byte Once the PC87570 is the active master of the ACCESS.bus (ACBST.MASTER is set), it can send the address on the bus. The address sent should not be the PC87570’s own ad- dress, as defined in ACBADDR.ADDR, if ACBADDR.SAEN is set, nor should it be the global call address if ACB- ST.GMTCH.GMTCH is set. ...
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... Whenever the ACB module is enabled, and it is not acting as a master (i.e., ACBST.MASTER is cleared), it acts as a slave device. Once a Start Condition on the bus is detected, the PC87570 checks whether the address sent by the current master matches either: The ACBADDR.ADDR value if ACBADDR.SAEN=1, or The general call address if ACBCTL1 ...
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... GMATCH are cleared, setting the module un- addressed slave. 13.3.3 Power-Down When the PC87570 is in Idle mode, the ACB module is not active but retains its status. If the ACB is enabled (ACBCTL2.ENABLE=1), on detection of a Start Condition, a wake-up signal is issued to the MIWU. This signal may be used to switch the PC87570 to Active mode ...
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Bit 3 - Stall After Start (STASTR) This bit is set by the successful completion of an ad- dress sending (i.e., a Start Condition sent without a bus error, or negative acknowledge), if ACBCTL1.STAS- TRE is set. This bit is ...
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... STASTRE NMINTE GCMEN ACK Res INTEN STOP START Bit 0 - START This bit should be set when a Start Condition needs to be generated on the ACCESS.bus the PC87570 is not the active master of the bus (ACBST.MASTER=0), setting START generates a Start Condition as soon as the ACCESS.bus is free (ACBCST.BB=0). An address transmission se- quence should then be performed. ...
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... Where t is the PC87570 clock cycle when in Active CLK mode (see Clock Output Signals in Table 19-9 on page 138). SCLFRQ may be programmed to values in the range of 0001000 (8 ) through 1111111 2 10 other value has unpredictable results. 13.5 USAGE HINTS 1. When the ACB is disabled, the ACBCST.BB bit is cleared ...
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Multi-Function 16-Bit Timer (MFT16) The MFT16 contains two independent 16-bit timer/counters. It can operate from several clock sources in Pulse Width Modulation (PWM), Capture or Counter mode in order to satisfy a wide range of application requirements. 14.1 FEATURES ...
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CLOCK SOURCE UNIT The clock source unit, Figure 14-2, contains two clock se- lectors for each counter and a 5-bit clock prescaler. 14.3.1 Prescaler The 5-bit clock prescaler consists of a prescaler register, and a 5-bit counter, allowing you ...
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Counter Clock Source Select The clock source unit contains two clock source selectors which allow you to independently select the clock source for each of the two 16-bit counters from one of the following sources: • No clock, in ...
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Mode 1, PWM and Counter PWM can be used to generate precise pulses of known width and duty cycle on the TA pin. The timer is clocked by the instruction clock. An underflow causes the timer register to be reloaded ...
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Mode 2, Dual Input Capture Dual capture mode can be used to precisely measure the frequency of an external clock that is slower than the select- ed clock source frequency measure the elapsed time between external events. A ...
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Mode 3, Dual Independent Timer Dual Independent Timer mode can be used for a wide vari- ety of system tasks such as the generation of period system interrupts, either based on the prescaled clock or external events on TB. The ...
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Mode 4, Input Capture and Timer It is also possible to operate in a mode which offers a com- bination of a single timer with automatic reload and a single capture timer. In this mode TCNT1 operates as a PWM-tim- ...
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Timer Interrupts The MFT16 contains a total of four interrupt sources which are mapped to two different system interrupts. All sources have a pending flag associated with them, and can be en- abled or disabled under software control. The ...
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MFT16 REGISTERS 14.5.1 Clock Prescaler Register (TPRSC) The TPRSC Register is a byte-wide read/write register. It contains the current value of the clock prescaler, CLKPS. The register is cleared on reset. It defines the timer clock prescaler ratio. 7 ...
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Bit Enable (TAEN) Enables TA to function either as a preset input PWM output, depending on the mode of operation. If the bit is set (1), while operating in the “Dual Input Capture” mode ...
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Timer and WATCHDOG (TWD) The TWD generates the clocks and interrupts used for tim- ing periodic functions in the system; it also provides WATCHDOG protection over software execution. The TWD provides flexibility in system configuration by en- abling the ...
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WATCHDOG OPERATION The WATCHDOG is an 8-bit down counter, operating on the rising edge of its currently selected clock source. Upon re- set disabled (i.e., it does not count and no WATCH- DOG signal is generated). A ...
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Bits 2-0 - Main Clock Divide (MDIV) Defines the pre-scale ratio of the input clock. The pre-scale MDIV ratio MDIV must be in the range of zero to five, pro- viding a pre-scale ratio ...
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... Analog MUX Comp _ DAC Int Ref ADC Config Control Logic AV CC INTREF other modules Figure 16-1. ADC Functional Diagram 119 capacitor during the sam- S ADC PC87570 Peripheral Bus Data Buffers Status and Control Registers ADCCLK System Clock Divider Clock Reset ...
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... Figure 16-1) allows ADC usage in systems with a higher clock rate. CDIV must be programmed prior to enabling the ADC (i.e., while ADCEN of the ADCCNT1 Register is 0). 16.2.5 Initializing and Enabling the ADC The PC87570 wakes up after power-up with the ADC dis- abled (ADCEN of the ADCCNT1 Register is cleared). In this . The ac- CC state, all ADC activities are halted, and its current consump- tion is reduced to zero ...
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... Disabling the ADC to Save Power When the ADC is not converting, it may be disabled to re- duce its current consumption from the AV 0.1 A. The PC87570 must first be placed in Idle mode, as described in Section 8.3.1. The decision to disable the ADC should be based on the ex- pected Idle mode period, as follows: If shorter than 100 s, the ADC should remain en- abled ...
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Analog to Digital Converter (ADC) - January 1998 16.3 OPERATION MODES The ADC supports four modes of automated operation, as defined by SCAN and CONT of the ADCCNT2 Register. Ta- ble 16-3 summarizes ADC operation in the various modes. Channel ...
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Analog to Digital Converter (ADC) - January 1998 16.4 ADC REGISTERS The ADC interfaces with the CR16A core, as shown in the "Block Diagram" on page 1. The interface is implemented by a set of four status and control registers, ...
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Analog to Digital Converter (ADC) - January 1998 Bits 2-0 - Analog Input Channel Select (CHANNEL) These bits control the input multiplexer and select the channel to be connected to the Sample and Hold block (see Figure 16-1). When using ...
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... AGND and higher, the chip may be damaged. External circuits should not drive currents into these pins when the PC87570 is not powered up. This may cause the internal power-up reset circuit to fail. 16.5.2 Power Consumption ADC power consumption from AV ADC is disabled by clearing the ADCEN bit of the ADCCNT1 Register ...
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Analog to Digital Converter (ADC) - January 1998 16.5.3 Filtering the Noise on Input Signals Input signals may be accompanied by unwanted noises caused by the digital circuits they pass nearby. Optionally, when converting slow changing signals in a noisy ...
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... Digital to Analog Converter (DAC 0 The DAC has a typi- PC87570 and is obtained * CC analog CC Figure 17-1. DAC Functional Diagram 17.2.3 Output Signal Range The DAC performs a linear conversion of the input digital value written into the DACDATA0-3 Registers to an un- signed analog output signal ...
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... Power Connection. The analog supply pin, AV connected to a low noise power supply with the same volt- age as the digital supply, either 3.3V or 5.0V. Both the digi- tal and analog power supplies of the PC87570 must be supplied simultaneously. To assure this, supply the AV pin from the digital V RC filter ...
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... higher, the chip CC may be damaged. External circuits should not drive currents into these pins when the PC87570 is not powered up. This may cause the internal power-up reset circuit to fail. 17.4.2 Output Settling Time The DAC output settling time depends on the external load characteristics and the required accuracy ...
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... PC87570 while mounted in the system. The TRIS input is a strap pin sampled at power-up reset. When TRIS is low (0), the PC87570 acts normally. When TRIS is high (1), all the PC87570 outputs are put to TRISTATE. Setting TRIS to the required value is described in Section 2.4 on page 26 18 ...
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Pipe Status Signals The Pipe Flow Signal (PFS) indicates the completion of an instruction in the CR16A. The Pipe Long Instruction (PLI) signal indicates the size of the completed instruction, where 0 = word instruction and 1 = double-word ...
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... This chapter provides power and grounding guidelines, specifies the maximum ratings and the electrical character- istics of the PC87570, and describes its timing. 19.1 POWER AND GROUNDING The PC87570 requires either a 5V +/- 10 3.3V +/- 10% supply to all four V pins. The digital ground pins of CC the PC87570 are marked GND ...
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Absolute Maximum Ratings Absolute maximum ratings are values beyond which damage to the device may occur. Continuous operation at these limits is not recommended. Unless otherwise specified, all voltages are relative to ground. Parameter Supply Voltage Input Voltage Output ...
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DC ELECTRICAL CHARACTERISTICS 19.3.1 Analog Parameter Symbol Internal Reference Voltage External Reference Voltage 2 V Input DC resistance REF Resolution 3 Integral (non-linearity) Error 4 Differential (non-linearity) Error Offset Error Gain Error Input Voltage Range Analog Input Leakage Current ...
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Digital Parameter TTL Input, Logical 0 Voltage TTL Input, Logical 1 Voltage CMOSS Input with Hysteresis (Schmidt), Logical 0 Voltage CMOSS Input with Hysteresis (Schmidt), Logical 1 Voltage CMOSS Input with Hysteresis (Schmidt), Hysteresis Loop Width STRAP Input, Logical ...
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Parameter CMHD2 Output, Logic 1, Voltage OD, Open-drain Output, Logical 0 Voltage OD2 Open-Drain Output, Logical 0 Voltage PU (Weak Pull-up), Logical 1, Output Voltage PU, Internal Pull-up Resistance Output Leakage Current (I/O pin in Input Mode) Digital Pin Capacitance ...
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AC ELECTRICAL CHARACTERISTICS The following abbreviations are used in this section Rising Edge FE = Falling Edge 19.4.1 Definitions The timing specifications in this section refer to low or high level voltage according to the specific buffer ...
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Timing Tables All output timings are guaranteed for 50 pF load, unless otherwise specified. Symbol Figure Description t 19-25 Valid time: External EPLv pull-up and pull-down resistors t 19-25 Internal power-on IRST reset time t 19-25 Supply wake-up time ...
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Symbol Figure Description t 19-8, Input setup time 1 19-10 D0-15 to 19-12 t 19-8, Input hold time 2 19-10 D0-15 to 19-12 t 19-8 Output valid time 3 to A0-17, BE0,1CBRD, 19-13 D0-15 t 19-8 Output valid time 4 ...
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Symbol Figure Description t 19-16 Read address valid AR t 19-17 Address valid to write AW active t 19-17 Write data hold DH t 19-17 Write data setup DS t 19-27 Host input signals HIPONh hold t 19-27 Host input ...
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Symbol Figure Description t 19-16 IOCHRDY inactive RDYA t 19-15 Input setup time PA0- INPs 6, PB0-7, PC0-7, PD0-7, PE0,1, PF0-7, PG0-4, PH0-5 t 19-15 Input hold time PA0- INPh 6, PB0-7, PC0-7, PD0-7, PE0-1, PF0-7, PG0-4, PH0-5 t 19-14 ...
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Symbol Figure Description t 19-21 SCL hold time CSTRhi t 19-21 SCL setup time CSTRsi t 19-21 Data high setup time Before SCL RE DHCsi t 19-20 Data low setup time DLCsi t 19-19 SDA signal fall time SCLfi t ...
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Symbol Figure Description t 19-22 SDA valid time SDAvo t 19-18 TA high time TAH t 19-18 TA low time TAL t 19-18 TB high time TBH t 19-18 TB low time TBL t 19-24 Input setup time Is ISE, ...
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TIMING DIAGRAMS 19.5.1 General V BAT t 32KX1/32KCLKIN 32KX2 V CC CLK Device Specifications 32KW Figure 19-5. 32K Waveforms 144 t 32KCLKIN 32KD www.national.com ...
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... Idle Mode www.national.com Device Specifications t CLK t t CLKr CLKf t t CLKl CLKh Input Setup Output Inactive Time Output Inactive Time Figure 19-6. Clock Waveforms t t CLKW CLKINTwk t CLKstab PC87570 in Active Mode Figure 19-7. Internal Clock Generator 145 Output Hold Input Hold t CLKINTst ...
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BIU Normal Read T1 T2 CLK t 3 t3, t12 A0-18 SELx t5, t12 t5, t12 SELy (y x) D0-15 In t5, t12 WR0,1 t4, t13 t4, t13 ...
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Bus State CLK A0-18 SELx (x y) SELy ( D0-15 RD WR0 BST0-2 Figure 19-9. Late Write between Two Normal Read Bus Cycles, 0 Wait, AC Timing Normal Read T1 CLK t ...
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Device Specifications Bus State T1 CLK t 3 A0- SELn, SELIO D0-15 RD WR0 BST0-2 Figure 19-11. Normal Read Bus Cycle (2 Internal Waits, and 1 Hold), AC Timing ...
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Figure 19-13. Core Bus Monitoring Bus Cycle, AC Timing 19.5.3 GPIO Ports CLK Px Output Signals Figure 19-14. Output Signal Timing for Output and I/O Port Signals www.national.com Device Specifications T1 CLK A0-12, ...
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CLK Px Input Signals Figure 19-15. Input Signal Timing for Input and I/O Port Signals 19.5.4 Host Interface 1 HAEN HMEMCS HA0-18 HIORD 1 HMEMRD HIOWR HMEMWR HD0-7 IRQ1, IRQ12 IRQ11 HIOCHRDY 1. Either HIORD or HMEMRD is active, for ...
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HAEN HMEMCS A0-A18 1 HIOWR HMEMWR HIORD HMEMRD HD0-7 HIOCHRDY Notes: 1. Either HIOWR or HMEMWR is active, for access to I/O devices or the shared memory, respectively. 19.5.5 MFT16 CLK TnA/TnB Figure 19-18. Multi-Function Timer (MFT16) Input Timing www.national.com ...
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ACCESS Bus Interface In the diagrams below, an “o” is added to parameter names in the timing tables for output signals, and an “i” for input signals. 0.7V SDA CC 0.3V CC 0.7V SCL 0.3V Figure 19-19. ACB Signals ...
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SDA SCL 19.5.7 Dev Environment Support CLK PFS PLI Figure 19-23. Pipe Status Signal (PFS and PLI) Timing 19.5.8 Interrupts and Wake-up CLK ISE, PFAIL, EXINTn HMEMRD HMEMWR PSCLK1-3 PSDAT1-3 KBSIN0-7 Figure 19-24. ISE, PFAIL, EXINTn and MIWU Input Signal ...
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Reset 1 V (Power) CC Internal WATCHDOG 1 Reset CLK Internal Reset 2 Internal Pull-ups & Pull-downs 2 External Pull-ups & Pull-downs 3 HPWRON Notes: 1. Either WATCHDOG or power-up. 2. Valid on power-up reset only. 3. HPWRON should ...
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... PS/2 Interface PSCLK1-3 PSDAT1-3 t PSCLK1-3 PSDAT1-3 CLK PSCLK1-3 Figure 19-30. PS/2 Clock Signal Pulled Low by PC87570 www.national.com Device Specifications t PSCLKl t PSDIs PSDIh Figure 19-28. PS/2 Receive Timing t PSCLKl t PSDOv Figure 19-29. PS/2 Transmit Timing t PSCLKa 155 t PSCLKh t PSCLKh t PSCLKia ...
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A. CR16A Register Map ACB Interface ACBSDA ACBST SLVSTP SDAST BER ACBCST Reserved TGSCL ACBCTL1 STASTRE NMINTE GCMEN ACBADDR SAEN ACBCTL2 ADC ADCST Reserved BUFPTR ADCCNT1 Reserved ADCCNT2 START SCAN ADCCNT3 Reserved ADDATA0 ADDATA1 ...
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BIU BCFG IOCFG Reserved IPST SZCFG0 Res FRE IPRE IPST SZCFG1 Res FRE IPRE IPST Configuration MCFG Reserved CLKOE PAGE Reserved STRPST Reserved DAC DACCTRL Reserved DACDAT0 DACDAT1 DACDAT2 ...
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GPIO Ports PADIR Res PADIN Res PADOUT Res PAWPU Res PBDIR Res PBDIN Res PBDOUT Res PBWPU Res PBALT PBALT.7 1 PCDIR Res PCDIN Res PCDOUT Res PCWPU Res PCALT Res PDDIN Res PDALT Res PEDIR ...
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GPIO Ports (Cont’d) PFDIR Res PFDIN Res PFDOUT Res PGDIR Reserved PGDIN Reserved PGDOUT Reserved PHDIR Reserved PHDIN Reserved PHDOUT Reserved HFCG HFCGCTRL Reserved HFCGML HFCGMH Reserved HFCGN Reserved HFCGIL HFCGIH Reserved 5 ...
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Host Interface CST1 Reserved CST2 Reserved RTCCA RTCCD HCFGBAL HCFGBAH HICTRL Reserved PMICIE PMECIE HIIRQC PSPE IRQNPOL HIKMST ST3 ST2 ST1 HIKDO Keyboard Channel DBBOUT Data HIMDO HIKMDI Keyboard/Mouse Channel DBBIN Data HIPMST ST3 ST2 ST1 HIPMDO ...
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ICU IVCT Reserved IELTG INT15-8 INT7 INT6 ITRPL INT15-8 INT7 INT6 IPEND INT15-8 INT7 INT6 IENAM INT15-8 INT7 INT6 IECLR INT15-8 INT7 INT6 NMISTAT PFAIL MFT16 TCNT1 TCRA TCRB TCNT2 TPRSC Reserved ...
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MIWU WKEDG1 WKED17 WKED16 WKED15 WKEDG2 WKED27 WKED26 WKED25 WKEDG3 WKED37 WKED36 WKED35 WKPND1 WKPD17 WKPD16 WKPD15 WKPCL1 WKCL17 WKCL16 WKCL15 WKPND2 WKPD27 WKPD26 WKPD25 WKPCL2 WKCL27 WKCL26 WKCL25 WKPND3 WKPD37 WKPD36 WKPD35 WKPCL3 WKCL37 WKCL36 WKCL35 ...
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PMC PMCSR Reserved EIM PS/2 Interface PSDAT PSTAT Reserved RFERR PSCON WPUEN IDB PSOSIG Reserved CLK3 PSISIG Reserved RCLK3 PSIEN Reserved TWD TWCFG Reserved WDSDME TWCP Reserved TWDT0 T0CSR Reserved WDCNT ...
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... B.1 OVERVIEW The bootloader program resides in the 2K on-chip ROM of the PC87570. It provides for an orderly transfer to the BIOS program, which resides in off-chip Flash, after power-up or reset. The bootloader program reads the configuration and strap pin settings after reset, and combines this information ...
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Pin No. Name Type 176-Pin 160-Pin TQFP PQFP PH.3 Input 101 91 PC.0 Output 61 55 B.3.2 On-Chip RAM On-chip RAM is used for variable storage, interrupt dispatch table and stack usage. The addresses used are: F000h - F00Fh variables ...
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If STRPST.SHBM = 1 (read Strap Register, Shared BIOS Memory bit) Set MCFG.SHMEM (Enable Shared BIOS Memory access) If KBC Header Signature not valid or KBC code size equal 0 Jump to KBC_Mem_Fail (bytes 0 & signature, byte ...
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... Thin Quad Flatpack (TQFP) Order Number PC87570-ICC/VPC NS Package Number VPC176 ...
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... PC87570 Keyboard and Power Management Controller Physical Dimensions All dimensions are in millimeters. LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1 ...