PC97307 National Semiconductor, PC97307 Datasheet
PC97307
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PC97307 Summary of contents
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... PC87307/PC97307 Plug and Play Compatible and PC97 Compliant SuperI/O Highlights General Description The PC87307/PC97307 (VUL) are functionally identical parts that offer a single-chip solution to the most commonly ® used ISA, EISA and MicroChannel peripherals. This fully Plug and Play (PnP) compatible chip incorporates a Floppy ...
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A special Plug and Play (PnP) module that includes: — Flexible IRQs, DMAs and base addresses that meet the Plug and Play requirements specified by Mi- ® crosoft in their 1995 hardware design guide for ® Windows and Plug and ...
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Software or hardware control — 13 IRQ channel options — Four 8-bit DMA channel options — Demand mode DMA support — An Enhanced Parallel Port (EPP) that is compatible with the new version EPP 1.9, and is IEEE1284 compliant ...
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... Highlights General Keyboard I/O Purpose Registers Interface X1 MR AEN A15-0 D7-0 DTR1/BOUT1 RD WR IOCHRDY ZWS IRQ1 IRQ12-3 IRQ15-14 DRQ3-0 DACK3-0 TC PC87307/PC97307 XDRD DTR2/BOUT2 XDCS XD7-0 PD7-0 SLIN/ASTRB STB/WRITE AFD/DSTRB INIT ACK ERR SLCT PE BUSY/WAIT BADDR1,0 CFG3-0 SELCS X1C 4 WDO Power ...
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... SuperI/O Configuration 2 Register, Index 22h ............................................................. 35 2.4.5 Programmable Chip Select Configuration Index Register, Index 23h ......................... 35 2.4.6 Programmable Chip Select Configuration Data Register, Index 24h .......................... 36 2.4.7 SRID Register (In PC97307 only) ................................................................................ 36 2.5 KBC CONFIGURATION REGISTER (LOGICAL DEVICE 0) .................................................... 36 2.5.1 SuperI/O KBC Configuration Register, Index F0h ....................................................... 36 2.6 FDC CONFIGURATION REGISTERS (LOGICAL DEVICE 3) ...
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... EXTERNAL I/O INTERFACES .................................................................................................. 46 3.4.1 Keyboard and Mouse Interface ................................................................................... 46 3.4.2 General Purpose I/O Signals ....................................................................................... 46 3.5 INTERNAL KBC - PC87307/PC97307 INTERFACE ................................................................. 47 3.5.1 The KBC DBBOUT Register, Offset 60h, Read Only .................................................. 47 3.5.2 The KBC DBBIN Register, Offset 60h (F1 Clear) or 64h (F1 Set), Write Only ............ 47 3.5.3 The KBC STATUS Register, Offset 64h, Read Only ................................................... 48 3 ...
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APC REGISTERS ...................................................................................................................... 60 4.5.1 APC Control Register 1 (APCR1), Index 40h .............................................................. 60 4.5.2 APC Control Register 2 (APCR2), Index 41h .............................................................. 61 4.5.3 APC Status Register (APSR), Index 42h ..................................................................... 61 4.5.4 RAM Lock Register (RLR), Index ...
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... The VERSION Command .......................................................................................... 108 5.7.24 The WRITE DATA Command .................................................................................... 108 5.7.25 The WRITE DELETED DATA Command .................................................................. 109 5.8 EXAMPLE OF A FOUR-DRIVE CIRCUIT USING THE PC87307/PC97307 ........................... 110 Parallel Port (Logical Device 4) 6.0 6.1 PARALLEL PORT CONFIGURATION .................................................................................... 111 6.1.1 Parallel Port Operation Modes .................................................................................. 111 6 ...
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EPP Data Register 1 (DATA1), Offset 05h ................................................................ 116 6.3.8 EPP Data Register 2 (DATA2), Offset 06h ................................................................ 116 6.3.9 EPP Data Register 3 (DATA3), Offset 07h ................................................................ 117 6.3.10 EPP Mode Transfer Operations ................................................................................ 117 6.3.11 EPP 1.7 ...
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Consumer IR Mode ................................................................................................... 135 7.3 REGISTER BANK OVERVIEW ............................................................................................... 136 7.4 UART MODES – DETAILED DESCRIPTION .......................................................................... 136 7.4.1 16450 or 16550 UART Mode ..................................................................................... 137 7.4.2 Extended UART Mode ............................................................................................... 137 7.5 SHARP-IR MODE – DETAILED DESCRIPTION ...
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Shadow of FIFO Control Register (SH_FCR), Bank 3, Offset 02h ............................ 157 7.13.4 Link Control Register (LCR) and Bank Select Register (BSR), Bank 3, Offset 03h .. 157 7.14 BANK 4 – IR MODE SETUP REGISTER ................................................................................ 157 7.14.1 ...
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Power Management Control 3 Register (PMC3), Index 04h ..................................... 175 9.2.8 Watchdog Time-Out (WDTO) Register, Index 05h .................................................... 175 9.2.9 WATCHDOG Configuration Register (WDCF), Index 06h ........................................ 175 9.2.10 WATCHDOG Status Register (WDST), Index 07h .................................................... 176 9.3 POWER ...
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Group 20 .................................................................................................................... 190 13.2.21 Group 21 .................................................................................................................... 190 13.2.22 Group 22 .................................................................................................................... 191 13.2.23 Group 23 .................................................................................................................... 191 13.3 AC ELECTRICAL CHARACTERISTICS .................................................................................. 191 13.3.1 AC Test Conditions 13.3.2 Clock ...
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... GPIO16 GPIO17/WDO GPIO20/IRSL1/ID1 GPIO21/IRSL2/IRSL0/ID2 GPIO22/POR 160 GPIO23/RING 1 5 www.national.com Signal/Pin Connection and Description 110 105 100 95 PC87307/PC97307 PlasticQuad Flatpack (PQFP), EIAJ Order Number PC87307VUL/PC97307VUL See NS Package Number VUL160A IRRX1 80 IRRX2/IRSL0/ID0 IRSL1/XD7/ID1 IRSL2/XD6/SELCS/GPIO21 GPIO27/XD5 75 GPIO26/XD4 GPIO25/XD3 GPIO24/XD2 CS2/XD1 CS1/XD0 70 XDRD/ID3 RING/XDCS CS0/CSOUT-NSC-Test ...
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SIGNAL/PIN DESCRIPTIONS Table 1-1 lists the signals of the part in alphabetical order and shows the pin(s) associated with each. Table 1-2 on page 23 lists the X-Bus Data Buffer (XDB) signals that are multiplexed and Table 1-3 on ...
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... CS0 is an open-drain pin that is in TRI-STATE unless V CS2 is multiplexed with XD1, CS1 is multiplexed with XD0, and CS0 is multiplexed with CSOUT-NSC-Test. Output Chip Select Read Output, NSC-Test – National Semiconductor test output. This is an open-drain output signal. Group 21 This signal is multiplexed with CS0. ...
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Signal/Pin Pin Module Name Number DIR 90 FDC DR1,0 88, 87 FDC DRATE0 84 FDC DRQ3-0 55-52 ISA-Bus DSKCHG 99 FDC DSR2,1 143, 133 UART1, UART2 DSTRB 119 Parallel Port DTR2,1 144, 134 UART1, UART2 ERR 116 Parallel Port GPIO17-10 ...
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Signal/Pin Pin Module Name Number GPIO20 157 General Purpose GPIO21 77, 158 GPIO22 159 GPIO23 160 GPIO27-24 76-73 HDSEL 92 FDC ID0 79 UART2 ID1 78 or 157 ID2 158 ID3 70 INDEX 97 FDC INIT 117 Parallel Port IOCHRDY ...
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Signal/Pin Pin Module Name Number IRTX 81 UART2 (SIR) KBCLK 102 KBC KBDAT 103 KBC MCLK 104 KBC MDAT 105 KBC MR 51 ISA-Bus MSEN1,0 83, 82 FDC MTR1,0 86, 85 FDC ONCTL 67 APC P17,16 108, 107 KBC P12 ...
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... SuperI/O Configuration 1 register (index 21h). Group internal pull-up resistor ( resistor for National Semiconductor testing) controls this pin during reset. Do not pull this signal low during reset. This signal is multiplexed with GPIO21, IRSL2 and XD6. Input Serial Input – This input signal receives composite serial data from ...
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Signal/Pin Pin Module Name Number SOUT2,1 148, 138 UART1, UART2 STB 112 Parallel Port STEP 91 FDC SWITCH 66 APC TC 35 ISA-Bus TRK0 96 FDC V 64 RTC and BAT APC V 65 RTC and CCH APC V 1, ...
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Signal/Pin Pin Module Name Number WGATE 93 FDC WP 98 FDC WR 34 ISA-Bus WRITE 112 Parallel Port X1 50 Clock X1C 62 RTC X2C 63 RTC XD7,6, 78, 77 X-Bus XD1,0 72, 71 XD5-2 76-73 X-Bus XDCS 69 X-Bus ...
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In Table 1-2, unselected (XDB or alternate function) input signals are internally blocked high. TABLE 1-2. Multiplexed X-Bus Data Buffer (XDB) Pins X-Bus Data Buffer (XDB) Pin Bit 4 of SuperI/O Configuration Register XDCS 70 XDRD ...
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Configuration The part is partially configured by hardware, during reset. The configuration can also be changed by software, by changing the values of the configuration registers. The configuration registers are accessed using an Index register and a Data register. ...
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The Strap Pins Pin CFG0 0 - FDC, KBC and RTC wake up inactive FDC, KBC and RTC wake up active. CFG1 X-Bus Data Buffer. (See XDB pins multiplexing in Table 1-2 ...
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TABLE 2-4. Parallel Port Address Range Allocation Parallel Port Mode SPP EPP (Non ECP Mode 4) ECP, No Mode 4, No Internal Configuration ECP with Mode 4, No Internal Configuration ECP with Mode 4, Configuration within Parallel Port a. The ...
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Standard Plug and Play (PnP) Register Definitions Tables 2-5 through 2-10 describe the standard Plug and Play registers. For more detailed information on these registers, refer the “Plug and Play ISA Specification, Version 1.0a, May 5, 1994.” . TABLE ...
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TABLE 2-6. PnP Logical Device Control Registers Index Name 0030h Activate 0031h I/O Range Check TABLE 2-7. PnP I/O Space Configuration Registers Index Name 60h I/O Port Base Read/write value indicating the selected I/O lower limit address bits 15-8 for ...
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TABLE 2-8. PnP Interrupt Configuration Registers Index Name 70h Interrupt Request Read/write value indicating selected interrupt level. Level Select 0 Bits3-0 select the interrupt level used for interrupt 0. A value of 1 selects IRQL 1, a value of 15 ...
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... PnP ISA Configuration Control. PnP ISA Wake[CSN]. Resource Data. Status. PnP ISA Card Select Number (CSN). PnP ISA Logical Device Number. SRID Register (in pc97307 only). Soft Reset 00h or 01h Activate. See CFG0,Section See also FER1 of power management device (logical device 8). ...
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TABLE 2-13. KBC Configuration Registers for Mouse - Logical Device 1 Index R/W Hard Reset Soft Reset 30h R/W 00h 00h 70h R/W 0Ch 0Ch 71h R/W 02h 02h 74h R 04h 04h 75h R 04h 04h TABLE 2-14. RTC ...
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TABLE 2-15. FDC Configuration Registers - Logical Device 3 Index R/W Hard Reset 30h R/W 00h or 01h See CFG0 in Section 2.1.3. 31h R/W 00h 60h R/W 03h 61h R/W F2h 70h R/W 06h 71h R/W 03h 74h R/W ...
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TABLE 2-17. UART2 and Infrared Configuration Registers - Logical Device 5 Index R/W Hard Reset 30h R/W 00h 31h R/W 00h 60h R/W 02h 61h R/W F8h 70h R/W 03h 71h R/W 03h 74h R/W 04h 75h R/W 04h F0h ...
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... Base Address Most Significant Byte. 00h Base Address LSB Register. Bit 0 (for A) is read only: 0. 04h Report no DMA assignment. 04h Report no DMA assignment. 2.4.2 SID Register (In PC97307) This read-only register holds the identity number of the chip. The PC97307VUL is identified by the value CFh in this reg- ister ...
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Bit 0 - ZWS Enable This bit controls assertion of ZWS on any host SuperI/O chip access, except for configuration registers access (including Serial Isolation register) and except for Paral- lel Port access. For ZWS assertion on host-EPP access, see ...
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... Reset Required Data in a Programmable Chip Select Configuration Register FIGURE 2-6. Programmable Chip Select Configuration Data Register Bitmap 2.4.7 SRID Register (In PC97307 only) This read-only register contains the identity number of the chip revision. SRID is incremented on each tapeout Reset Required Chip Revision ID FIGURE 2-7 ...
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Bit 0 - TRI-STATE Control When set, this bit causes the FDC pins TRI- STATE (except the IRQ and DMA pins) when the FDC is inactive (disabled). This bit is ORed with a bit of PMC1 register ...
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This option supports run-time configuration within the Parallel Port address space. An 8-byte (and 1024-byte) aligned base address is required to ac- cess these registers. See Chapter 6 on page 111 for details. Bit 7-5 - Parallel Port Mode Select ...
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PROGRAMMABLE CHIP SELECT CONFIGURATION REGISTERS The chip select configuration registers are accessed using two index levels. The first index level accesses the Pro- grammable Chip Select Index register at 23h. See Section 2.4.5 on page 35. The second index ...
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CS1 Base Address MSB Register, Second Level Index 04h This read/write register is reset by hardware to 00h. Same as Plug and Play ISA base address register at index 60h. See Table 2-7 on page 28. 2.10.6 CS1 Base ...
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... Reset Index 23h Required Index of a Programmable Chip Select Configuration Register Programmable Chip Select Configuration Data Register Reset Index 24h Required Data in a Programmable Chip Select Configuration Register SRID (in PC97307 only Register Reset Index 27h Required Chip Revision ID SuperI/O KBC Configuration ...
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Reset Required TRI-STATE Control Reserved DENSEL Polarity Control TDR Register Mode Four Drive Control ...
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... KBC firmware as shown in Figure 3-1. Program Address Program ROM TEST1 Timer Overflow 8-Bit Timer STATUS or Counter IBF P27, P26, P23, P22 TEST0 Drivers KBCLK MDAT MCLK 43 Data RAM 256 x 8 (including registers and stack) DBBIN DBBOUT D7 PC87307/PC97307 Interface www.national.com A2 ...
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... External I/O interface • Internal KBC - PC87307/PC97307 interface • PC87307/PC97307 - PC chip set interface. These system interfaces are shown in Figure 3-2. The KBC uses two data registers (for input and output) and a status register to communicate with the part central sys- tem. Data exchange between these units may be based on programmed I/O or interrupt-driven ...
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... FIGURE 3-3. Interrupt Request Logic Instruction Cycle = 15 Clock Cycles FIGURE 3-4. Instruction Timing External Clock Standard or Open-Collector TTL Driver FIGURE 3-5. External Clock Connection 45 Interrupt Plug and Polarity Play Matrix (0 = Invert MUX Interrupt Plug and Polarity Play Matrix (0 = Invert MUX PC87307/PC97307 www.national.com ...
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Keyboard (and Mouse) Controller (KBC) (Logical Devices 0 and 1) External MHz X1 Clock Frequency External X1C Multiplier 32768 Hz Crystal X2C (1465) (MCLK) FIGURE 3-6. Timing Generation and Timer Circuit 3.3.4 Timer or Event Counter The ...
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... P20 and P21 are driven by open-drain drivers. When the KBC is reset, all port data bits are initialized to 1. 3.5 INTERNAL KBC - PC87307/PC97307 INTERFACE The KBC interfaces internally with the part via three regis- ters: an input (DBBIN), output (DBBOUT) and status (STA- TUS) register ...
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Keyboard (and Mouse) Controller (KBC) (Logical Devices 0 and 1) 3.5.3 The KBC STATUS Register, Offset 64h, Read Only The STATUS register holds information regarding the sys- tem interface status. Figure 3-9 shows the bit definition of this register. This ...
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Real-Time Clock (RTC) and Advanced Power Control (APC) (Logical Device 2) 4.0 Real-Time Clock (RTC) and Advanced Power Control (APC) (Logical Device 2) The RTC logical device contains two major functions: the Real-Time Clock (RTC) and Advanced Power Control (APC). ...
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Real-Time Clock (RTC) and Advanced Power Control (APC) (Logical Device 2) • An external clock may be connected to pin X1C. The time generation function divides the 32.768 KHz derive signal which serves as ...
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... Host PC PC87307/ PC97307 RTC and APC Modules FIGURE 4-2. PC87307/PC97307 Power Supplies V CCH FIGURE 4-3. Typical Battery Configuration 4.1.3 Power Supply The host PC and part power is supplied by the system pow- er supply voltage, V Figure 4-2 shows the power supplies of the part. ...
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Real-Time Clock (RTC) and Advanced Power Control (APC) (Logical Device 2) System Bus Lockout As the RTC switches to battery power all, input signals are locked out so that the internal registers can not be modified externally. Power Up Detection ...
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Real-Time Clock (RTC) and Advanced Power Control (APC) (Logical Device 2) UIP bit of CRA UF bit of CRC D PF bit of CRC AF bit of CRC A-B Update In Progress (UIP) bit high before update occurs = 244 ...
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Real-Time Clock (RTC) and Advanced Power Control (APC) (Logical Device 2) 4.2.2 RTC Control Register B (CRB), Index 0Bh This register enables the selection of various time and date options, as well as the use of interrupts ...
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Real-Time Clock (RTC) and Advanced Power Control (APC) (Logical Device 2) Bit 7 - Interrupt Request Flag (IRQF) This read-only bit is the inverse of the value on the IRQ output signal of the RTC/APC IRQ is inactive ...
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... Off or Power Failure. These states are illustrated in Fig- ure 4-9 on page 57. Table 4-5 indicates the power-source combinations for each state. No other power-source combi- nations are valid. In addition, the power sources and distribution for the entire PC system are described in “PC87307/PC97307 Power Supplies” on page 51. TABLE 4-5. System Power States V V ...
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Real-Time Clock (RTC) and Advanced Power Control (APC) (Logical Device 2) APC Inactive ONCTL = Inactive APC Active Initial Values V V CCH Power Don’t Care BAT V = High CCH ONCTL = Active APC Active Programmed ...
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Real-Time Clock (RTC) and Advanced Power Control (APC) (Logical Device 2) 4.4 DETAILED FUNCTIONAL DESCRIPTION 4.4.1 The ONCTL Signal The APC checks when activation or deactivation conditions are met, and sets or resets the ONCTL signal accordingly. This signal activates ...
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Real-Time Clock (RTC) and Advanced Power Control (APC) (Logical Device 2) Power Off Request (POR) The APC allows a maskable or non-maskable interrupt on the POR pin when the Switch Off event is detected on the SWITCH input pin. This ...
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Real-Time Clock (RTC) and Advanced Power Control (APC) (Logical Device 2) Predetermined Wake-Up The second, minute and hour values of the pre-determined wake-up times are contained in the Seconds Alarm, Min- utes Alarm and Hours Alarm registers, respectively (index- es ...
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Real-Time Clock (RTC) and Advanced Power Control (APC) (Logical Device 2) 4.5.2 APC Control Register 2 (APCR2), Index 41h Power-Up Reset Required TME RSS RPTDM RE R1E R2E SODE Reserved FIGURE 4-12. ...
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Real-Time Clock (RTC) and Advanced Power Control (APC) (Logical Device 2) 4.5.4 RAM Lock Register (RLR), Index 47h Once a non-reserved bit is set can be cleared only by hardware (MR pin) reset ...
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Real-Time Clock (RTC) and Advanced Power Control (APC) (Logical Device 2) 4.6.2 APC Register Bitmaps Power-Up Reset Required Reserved Switch Off Delay Option POR Edge or Level Select Level POR Clear Command ...
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Real-Time Clock (RTC) and Advanced Power Control (APC) (Logical Device 2) 4.7 REGISTER BANK TABLES TABLE 4-6. Banks 1 and 2, Common 64-Byte Memory Map Index Function 00h Seconds 01h Seconds Alarm 02h Minutes 03h Minutes Alarm 04h Hours 05h ...
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Real-Time Clock (RTC) and Advanced Power Control (APC) (Logical Device 2) TABLE 4-8. Bank 1 Registers, RTC Memory Bank Register Index Type 00h-3Fh 40h-47h Century 48h R/W 49h-4Fh Upper RAM 50h R/W Address Port 51h-52h Upper RAM Data 53h R/W ...
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The Digital Floppy Disk Controller (FDC) (Logical Device 3) 5.0 The Digital Floppy Disk Controller (FDC) (Logical Device 3) The Floppy Disk Controller (FDC) is suitable for all PC-AT, EISA, PS/2, and general purpose applications. DP8473 and N82077 software compatibility ...
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... Motor Speed Variation (% of Nominal) Typical Performance at 500 Kbps 5 FIGURE 5-2. PC87307/PC97307 Dynamic Window Mar- gin Performance The x axis measures MSV. MSV is translated directly to the actual rate at which the data separator reads data from the disk. In other words, a faster than nominal motor results in a higher data rate ...
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The Digital Floppy Disk Controller (FDC) (Logical Device 3) The controller maximizes the internal digital data separator by implementing a read algorithm that enhances the lock characteristics of the fully digital Phase-Locked Loop (PLL). The algorithm minimizes the effect of ...
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The Digital Floppy Disk Controller (FDC) (Logical Device 3) 5.2.5 Write Precompensation Write precompensation enables the WDATA output signal to adjust for the effects of bit shift on the data written to the disk surface. Bit shift ...
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The Digital Floppy Disk Controller (FDC) (Logical Device 3) 5.3 THE REGISTERS OF THE FDC The FDC registers are mapped to the offset address shown in Table 5-1, with the base address range provided by the on-chip address decoder. For ...
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The Digital Floppy Disk Controller (FDC) (Logical Device 3) Bit 5 - Step This bit indicates whether or not the head of the Floppy Disk Drive (FDD) should move during a seek operation. Its value is the inverse of the ...
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The Digital Floppy Disk Controller (FDC) (Logical Device 3) TABLE 5-2. Drive and Motor Pin Encoding for Four Drive Configurations and Drive Exchange Support Control Digital Output Signals Register Bits MTR ...
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The Digital Floppy Disk Controller (FDC) (Logical Device 3) Bit 4- Motor Enable 0 If four drives are supported (bit 7 of the SuperI/O FDC Configuration register at index F0h is 1), this bit may control the motor output signal ...
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The Digital Floppy Disk Controller (FDC) (Logical Device 3) Bits 1,0 - Tape Drive Select 1,0 These bits assign a logical drive number to a tape drive. Drive 0 is not available as a tape drive and is reserved as ...
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The Digital Floppy Disk Controller (FDC) (Logical Device 3) Bit 2 - Drive 2 Busy This bit indicates whether or not drive 2 is busy set to 1 after the last byte of the command phase of a ...
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The Digital Floppy Disk Controller (FDC) (Logical Device 3) Track 0 is the default starting track number for precom- pensation. The starting track number can be changed using the CONFIGURE command. TABLE 5-7. Write Precompensation Delays DSR Bits Duration of ...
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The Digital Floppy Disk Controller (FDC) (Logical Device 3) The programmable FIFO threshold (THRESH) is useful in adjusting the FDC to the speed of the system. A slow sys- tem with a sluggish DMA transfer capability requires a high value ...
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The Digital Floppy Disk Controller (FDC) (Logical Device 3) 5.3.9 Configuration Control Register (CCR), Offset 07h, Write Operations This write-only register can be used to set the data transfer rate (in place of the DSR) for PC-AT, PS/2 and MicroChan- ...
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The Digital Floppy Disk Controller (FDC) (Logical Device 3) During DMA operations, FDC address signals are ignored since AEN input signal is 1. The DACK signal acts as the chip select signal for the FIFO, in this case, and the ...
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... Drive Polling Phase National Semiconductor’s FDC supports the polling mode of old 8-inch drives means of monitoring any change in status for each disk drive present in the system. This sup- port provides backward compatibility with software that ex- pects it ...
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The Digital Floppy Disk Controller (FDC) (Logical Device 3) The controller also uses the drive polling phase to automat- ically trigger power down. When the specified time that the motor may be off expires, the controller waits 512 msec, based ...
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The Digital Floppy Disk Controller (FDC) (Logical Device 3) Bit 1 - Drive Write Protected When a write or format command is issued, this bit indi- cates whether or not the selected drive is write protect- ed, i.e., the WP ...
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The Digital Floppy Disk Controller (FDC) (Logical Device 3) Bit 4 - Wrong Track This bit indicates whether or not there was a problem finding the sector because of the track number Sector found Desired sector ...
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The Digital Floppy Disk Controller (FDC) (Logical Device 3) 5.6 FDC REGISTER BITMAPS 5.6.1 FDC Standard Register Bitmaps PS/2 Drive Mode Reset Required Head Direction WP INDEX Head ...
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The Digital Floppy Disk Controller (FDC) (Logical Device 3) Read Operations, PC-AT Drive Mode Reset Required Reserved, In TRI-STATE DSKCHG Read Operations, PS/2 Drive Mode 7 6 ...
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THE FDC COMMAND SET The first command byte for each command in the FDC com- mand set is the opcode byte. The FDC uses this byte to de- termine how many command bytes to expect invalid command ...
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Abbreviations Used in FDC Commands BFR Buffer enable bit set in the MODE command. En- ables open-collector output buffers. BST Burst mode disable control bit set in MODE com- mand. Disables burst mode for the FIFO, if the FIFO ...
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WLD Wildcard bit in the MODE command used to enable or disable the wildcard byte (FFh) during scan com- mands. WNR Write Number controls whether to read an existing track number or to write a new one in the SET ...
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Byte of Present Track Number (PTR) Drive 0 Byte of Present Track Number (PTR) Drive 1 Byte of Present Track Number (PTR) Drive 2 Byte of Present Track Number (PTR) Drive 3 Step Rate Time ...
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TABLE 5-10. Typical Values for PC Compatible Diskette Media Bytes in Data Media Type Field (decimal) 360 KB 512 1.2 MB 512 720 KB 512 1.44 MB 512 c 512 2. Gap 2 is specified in the command ...
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Drive Type and Bytes in Data Bytes-Per-Sector Data Transfer Field (decimal) Rate 256 256 250 Kbps 512 MFM 512 1024 2048 4096 500 Kbps 256 MFM 512 512 1024 2048 4096 8192 a. Gap 2 is specified in the command ...
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Result Phase Result Phase Status Register 0 (ST0) Result Phase Status Register 1 (ST1) Result Phase Status Register 2 (ST2) Undefined Undefined Undefined Undefined 5.7.5 The INVALID Command If an invalid command (illegal opcode byte ...
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Bits 3,2 - Low-Power Mode (LOW PWR) These bits determine whether or not the FDC powers down and does, they specific how long it will take. These bits disable power down, i.e., are cleared to 0, af- ter ...
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Fourth Command Phase Byte Bits 3-0 - Head Settle Factor This field is used to specify the maximum time allowed for the read/write head to settle after a seek during an implied seek operation. The value specified by these bits ...
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If the system includes perpendicular drives, this command should be issued during initialization of the FDC. Then, when a drive is accessed for a FORMAT TRACK or WRITE DATA command, the FDC adjusts the command parame- ters based on the ...
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The READ DATA Command The READ DATA command reads logical sectors that con- tain a normal data address mark from the selected drive and makes the data available to the host microprocessor. Command Phase The READ DATA command phase ...
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Eighth Command Phase Byte - Bytes Between Sectors - Gap 3 The value in this byte specifies how many bytes there are between sectors. See “Fifth Command Phase Byte - Bytes in Gap 3” on page 90. Ninth Command Phase ...
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Result Phase Upon terminating the execution phase of the READ DATA command, the controller asserts IRQ6, indicating the begin- ning of the result phase. The microprocessor must then read the result bytes from the FIFO ...
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TABLE 5-19. SK Effect on READ DELETED DATA Command Skip Control Data Sector Control Mark Bit 6 Type Read? (SK) of ST2 0 Normal Deleted Normal Deleted Y 0 Result Phase ...
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The READ A TRACK Command The READ A TRACK command reads sectors from the se- lected drive, in physical order, and makes the data available to the host. Command Phase MFM 0 0 ...
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If the number of tracks on the disk drive exceeds the maxi- mum number of RECALIBRATE step pulses, it may be nec- essary to issue another RECALIBRATE command. TABLE 5-20. Maximum RECALIBRATE Step Pulses for Values of R255 and ETR ...
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SCAN LOW OR EQUAL MFM IPS Track Number Head Number Sector Number Bytes-Per-Sector Code End of Track (EOT) Sector Number Bytes Between Sectors - Gap 3 Sector ...
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Command Phase When bit 2 of the second command phase byte (ETR) in the MODE command is set to 1, the track number is stored as a 12-bit value. See “Bit 0 - Extended Track Range (ETR)” on page 92. ...
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TABLE 5-22. Interrupt Causes Reported by SENSE INTERRUPT Bits of ST0 Interrupt Cause FDC became ready during drive polling mode. SEEK, RELATIVE SEEK or RECALIBRATE not completed SEEK, RELATIVE SEEK or ...
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First Command Phase Byte, Bit 6 - Write Track Number (WNR Read the existing track number. The result phase byte already contains the track number, and the third byte in the command phase is a dummy byte. 1 ...
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TABLE 5-24. Constant Multipliers for Delay After Processing Factor and Delay Ranges Bit 7 of MODE (TMR Data Transfer Rate (bps) Constant Multiplier 500 K 16 300 250 K 32 TABLE ...
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Command Phase MFM Track Number Head Number Sector Number Bytes-Per-Sector Code End of Track (EOT) Sector Number Bytes Between Sectors - Gap 3 Sectors to read ...
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The VERSION Command The VERSION command returns the version number of the current Floppy Disk Controller (FDC). Command Phase Execution Phase None. Result Phase ...
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Overrun error. The Overrun bit (bit 4) in ST1 is set. The Interrupt Code (IC) bits (bits 7,6) in ST0 are set to abnor- mal termination (01). If the microprocessor cannot ser- vice a transfer request in time, the ...
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... EXAMPLE OF A FOUR-DRIVE CIRCUIT USING THE PC87307/PC97307 Figure 5-21 shows one implementation of a four-drive circuit. Refer to Table 5-2 on page 72 to see how to encode the drive and motor bits for this configuration. DR0 DR1 PC87307/ PC97307 MTR0 FIGURE 5-21. PC87307/PC97307 Four Floppy Disk Drive Circuit www ...
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Parallel Port (Logical Device 4) The Parallel Port is a communications device that transfers parallel data between the system and an external device. Originally designed to output data to an external printer, the use of this port has grown ...
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Configuration Operation Mode Time SPP Compatible Configuration at SPP Extended System Initialization EPP Revision 1.7 (Static) EPP Revision 1.9 SPP Compatible PP FIFO Configuration at System SPP Extended Initialization EPP Revision 1.7 with Run-Time EPP Revision 1.9 Reconfiguration (Dynamic) ECP(Default) ...
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Bit 5 of Mode RD WR CTR Data written to PD7- Data written is latched SPP Data read from output Extended Data read from PD7-0. In SPP Compatible ...
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Bit Status This bit reflects the current state of the printer paper end signal (PE). The printer sets this bit high when it detects the end of the paper Printer has paper End ...
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Bits 7,6 - Reserved These bits are reserved and are always 1. 6.3 ENHANCED PARALLEL PORT (EPP) MODES EPP modes allow greater throughput than SPP modes by supporting faster transfer times ( 32-bit data trans- fers in a ...
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SPP or EPP Control Register (CTR), Offset 02h This control port is read or write. A write operation to it sets the state of four pins on the 25-pin D-shell connector, and controls both the parallel port interrupt enable ...
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EPP Data Register 3 (DATA3), Offset 07h This is the fourth EPP data register only accessed to transfer bits 31 through 32-bit read or write to EPP Data Register 0 (DATA0 ...
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EPP 1.7 Data Write and Read This procedure writes to the selected peripheral device or register. EPP 1.7 data read or write operations are similar to EPP 1.7 Address register read or write operations, except that the data strobe (DSTRB ...
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D7-0 RD WAIT ASTRB WRITE PD7-0 IOCHRDY ZWS FIGURE 6-16. EPP 1.9 Address Read EPP 1.9 Data Write and (Backward) Data Read This procedure writes to the selected peripheral drive or register. EPP 1.9 data read and write operations are ...
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ECP MODE REGISTERS The ECP registers are each a byte wide, and are listed in Table 6-6 in order of their offsets from the base address of the parallel port. In addition, the ECP has control registers at second ...
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ECP Data Register (DATAR), Bits 7-5 of ECR = 000 or 001, Offset 000h The ECP Data Register (DATAR) register is the same as the DTR register (see Section 6.2.2), except that a read al- ways returns the values ...
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Bit 7 -Printer Status This bit reflects the inverse of the state of the BUSY sig- nal Printer is busy (cannot accept another character now Printer not busy (ready for another character). 6.5.6 ECP Control Register ...
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Reading from this register pops a byte from the FIFO. Writ- ing to this register when it is set for read-only has no effect, and the data written is ignored. Bits 7-5 of ECR = 011 ...
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Bits 1,0 - DMA Channel Select These bits reflect the value of bits 1,0 of the PP Config0 register (second level offset 05h). Microsoft’s ECP Pro- tocol and ISA Interface Standard defines these bits as shown in Table 6-7. Bits ...
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Bit 3 - ECP DMA Enable 0 - The DMA request signal (DRQ3-0) is set to TRI- STATE and the appropriate acknowledge signal (DACK3-0) is assumed inactive The DMA is enabled and the DMA starts when bit 2 ...
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ECP Extended Data Register (EDR), Offset 404h This read/write register is the data port of the control regis- ter indicated by the index stored in the EIR. Reading or writ- ing this register reads or writes the data in ...
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Bits 2-0 - Reserved These bits are reserved. Bit 3 - EPP 1.7 ZWS Control Upon reset this bit is initialized to 0. This bit controls as- sertion of ZWS on EPP 1.7 access. There is no ZWS assertion on ...
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Bits ECP DMA Channel Number These bits identify the ECP DMA channel number, as reflected on bits 1 and 0 of the ECP CNFGB register. See Section 6.5.11 on page 123. Actual ECP DMA rout- ing is ...
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ECP Mode ECP Mode (ECR Bits) Name Standard Write cycles are under software control. STB, AFD, INIT and SLIN are open-drain output signals. Bit 5 of DCR is forced to 0 (forward direction) and ...
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ECP (Backward) Read Cycle An ECP read cycle starts when the ECP drives AFD low. The peripheral device drives BUSY high for a normal data read cycle, or drives BUSY low for a command read cycle, and drives the byte ...
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PARALLEL PORT REGISTER BITMAPS 6.7.1 EPP Modes Parallel Port Register Bitmaps Reset Required Data Bits D6 D7 ...
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ECP Modes Parallel Port Register Bitmaps Bits 7-5 of ECR = 000 or 001 Reset Required Data Bits ...
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Bits 7-5 of ECR = 111 Configuration Register Reset Required DMA Channel Select Reserved Interrupt Select IRQ Signal Value Reserved ...
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Reset Required ECP DMA Channel Number PE Internal Pull-up or Pull-down ECP IRQ Number Demand DMA Enable Bit 3 of CNFGA www.national.com Parallel Port ...
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UART1 and UART2 (with IR) (Logical Devices 5 and 6) 7.0 UART1 and UART2 (with IR) (Logical Devices 5 and 6) This section describes the functionality of the Legacy UART (16450/16550), Enhanced UART and the IR modes. UART1 supports standard ...
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UART1 and UART2 (with IR) (Logical Devices 5 and 6) 7.3 REGISTER BANK OVERVIEW Eight register banks, each containing eight registers, con- trol UART operation. All registers use the same 8-byte ad- dress space to indicate offsets 00h through 07h, ...
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UART1 and UART2 (with IR) (Logical Devices 5 and 6) The module provides receive and transmit channels that can operate concurrently in full-duplex mode. This module performs all functions required to conduct parallel data in- terchange with the system and ...
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UART1 and UART2 (with IR) (Logical Devices 5 and 6) 7.5 SHARP-IR MODE – DETAILED DESCRIPTION This mode supports bidirectional data communication with a remote device using infrared radiation as the transmission medium. Sharp-IR uses Digital Amplitude Shift Keying (DASK) ...
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UART1 and UART2 (with IR) (Logical Devices 5 and 6) comes active only if the frequency is within the programmed range. Otherwise, the signal is ignored and no other action is taken. When the receiver enters the active state, the ...
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UART1 and UART2 (with IR) (Logical Devices 5 and 6) internal flag is cleared. The internal flag is also cleared and the transmitter starts transmitting when a time-out condition is reached. This prevents some bytes from being in the TX_FIFO ...
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UART1 and UART2 (with IR) (Logical Devices 5 and 6) 7.11.1 Receiver Data Port (RXD) or the Transmitter Data Port (TXD), Bank 0, Offset 00h These ports share the same address. RXD is accessed during CPU read cycles ...
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UART1 and UART2 (with IR) (Logical Devices 5 and 6) Interrupt Enable Register (IER), in the Non-Extended Modes (UART, SIR and Sharp-IR) Upon reset, the IER supports UART, SIR and Sharp-IR in the Non-Extended modes. Figure 7-5 shows the bitmap ...
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UART1 and UART2 (with IR) (Logical Devices 5 and 6) Bit 5 - Transmitter Empty Interrupt Enable (TXEMP_IE) Setting this bit enables interrupt generation if the trans- mitter and TX_FIFO become empty Disable Transmitter Empty interrupts (Default) 1 ...
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UART1 and UART2 (with IR) (Logical Devices 5 and 6) TABLE 7-3. Non-Extended Mode Interrupt Priorities EIR Bits Priority Interrupt Type Level None Highest Link Status 0 ...
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UART1 and UART2 (with IR) (Logical Devices 5 and 6) TABLE 7-4. Modem Status Event Detection Enable IRMSSL Value Bit Function 0 Modem Status Event (MS_EV) 1 Forced to 0. Bit 4 - DMA Event Occurred (DMA_EV) When an 8237 ...
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UART1 and UART2 (with IR) (Logical Devices 5 and 6) Link Control Register (LCR), All Banks, Offset 03h Bits 6-0 are only effective in UART, Sharp-IR and SIR modes. They are ignored in Consumer-IR mode ...
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UART1 and UART2 (with IR) (Logical Devices 5 and 6) 7.11.6 Bank Selection Register (BSR), All Banks, Offset 03h Reset Required Bank Selection BKSE-Bank ...
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UART1 and UART2 (with IR) (Logical Devices 5 and 6) Modem/Mode Control Register (MCR), Extended Mode, Bank 0, Offset 04h In Extended mode, this register is used to select the opera- tion mode (IrDA, Sharp, etc.) of the device and ...
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UART1 and UART2 (with IR) (Logical Devices 5 and 6) Bit 1 - Overrun Error (OE) This bit is set soon as an overrun condition is de- tected by the receiver. Cleared upon read. With FIFOs Disabled: ...
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UART1 and UART2 (with IR) (Logical Devices 5 and Reset Required DCTS DDSR TERI DDCD CTS DSR RI DCD FIGURE 7-16. MSR Register ...
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UART1 and UART2 (with IR) (Logical Devices 5 and 6) Bit 2 - Set End of Transmission (S_EOT) In Consumer-IR mode this is the Set End of Transmis- sion bit. When written into this bit position before ...
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UART1 and UART2 (with IR) (Logical Devices 5 and 6) TABLE 7-12. Bits Cleared On Fallback UART Mode & LOCK bit before Fallback Extended Non-Extended Register Mode Mode LOCK = x LOCK = 0 MCR none EXCR1 ...
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UART1 and UART2 (with IR) (Logical Devices 5 and 6) TABLE 7-14. Baud Generator Divisor Settings Prescaler Value 13 Baud Rate Divisor % Error 50 2304 0.16% 75 1536 0.16% 110 1047 0.19% 134.5 857 0.10% 150 768 0.16% 300 ...
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UART1 and UART2 (with IR) (Logical Devices 5 and 6) 7.12.2 Extended Control Register 1 (EXCR1), Bank 2, Offset 02h Use this register to control module operation in the Extend- ed mode. Upon reset all bits are set to 0. ...
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UART1 and UART2 (with IR) (Logical Devices 5 and 6) 5. The modem status input pins (DSR, CTS, RI and DCD) are disconnected. The internal modem status signals, are driven by the lower bits of the MCR register. Bit 5 ...
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UART1 and UART2 (with IR) (Logical Devices 5 and 6) Extended Modes Reset 0 0 Required TFL0 TFL1 TFL2 TFL3 TFL4 TFL5 Reserved Reserved ...
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UART1 and UART2 (with IR) (Logical Devices 5 and 6) 7.13.2 Shadow of Link Control Register (SH_LCR), Bank 3, Offset 01h This register returns the value of the LCR register. The LCR register is written into when a byte value ...
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UART1 and UART2 (with IR) (Logical Devices 5 and 6) TABLE 7-21. Sharp-IR or SIR Mode Selection IR_SL1 IR_SL0 Selected Mode 0 0 UART (Default Bits 7-4 - Reserved Read/Write 0. 7.14.3 Link Control ...
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UART1 and UART2 (with IR) (Logical Devices 5 and 6) 7.16 BANK 6 – INFRARED PHYSICAL LAYER CONFIGURATION REGISTERS This Bank of registers controls aspects of the framing and timing of the infrared modes. TABLE 7-23. Bank 6 Register Set ...
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UART1 and UART2 (with IR) (Logical Devices 5 and 6) Register Offset Description Name 05h Reserved 06h IRCFG3 Infrared Interface Configuration Register 3 07h IRCFG4 Infrared Interface Configuration Register 4 The Consumer-IR utilizes two carrier frequency ranges (see also Table ...
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UART1 and UART2 (with IR) (Logical Devices 5 and 6) TABLE 7-25. Consumer-IR, Low Speed Demodulator (RXHSC = 0) (Frequency Ranges in KHz) DFR Bits min/max min 26. ...
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UART1 and UART2 (with IR) (Logical Devices 5 and 6) TABLE 7-26. Consumer IR, High Speed Demodulator (RXHSC = 1) (Frequency Ranges in kHz) DFR Bits min/max min 380. ...
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UART1 and UART2 (with IR) (Logical Devices 5 and 6) 7.17.3 Consumer-IR Configuration Register (RCCFG), Bank 7, Offset 02h This register control the basic operation of the Consumer- IR mode. After reset, the content of this register is 00h. Consumer-IR ...
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UART1 and UART2 (with IR) (Logical Devices 5 and 6) If ID0/IRSL0/IRXX2 is programmed as an output (IRSL0_DS = 1), then: — If AMCFG (bit 7 of IRCFG4) is set to 1, this bit drives the ID0/IRSL0/IRRX2 pin when Sharp-IR ...
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UART1 and UART2 (with IR) (Logical Devices 5 and 6) Bits 2-0 - Reserved Read/write 0. Bit 3- ID/IRSL(2-1) Pins’ Direction Select (IRSL21_DS) This bit determines the direction of the ID/IRSL2 and ID/IRSL1 pins Pins’ direction is input. ...
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UART1 and UART2 (with IR) (Logical Devices 5 and 6) Extended Mode, Read Cycles Reset Required RXHDL_EV TXLDL_EV LS_EV or TXHLT_EV MS_EV DMA_EV TXEMP-EV ...
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UART1 and UART2 (with IR) (Logical Devices 5 and 6) Non-Extended Mode Reset Required Scratch Data Extended UART, SIR or Sharp-IR Mode ...
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UART1 and UART2 (with IR) (Logical Devices 5 and 6) IrDA or Consumer-IR Modes Reset 0 0 Required TFL0 TFL1 TFL2 TFL3 TFL4 TFL5 ...
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UART1 and UART2 (with IR) (Logical Devices 5 and Reset Required SPW(3-0) Reserved Infrared Receiver Demodulation Control 7 6 ...
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... GPIO20 is multiplexed with IRSL1. • GPIO17 is multiplexed with WDO A GPIO port must not be enabled at the same address as another accessible PC87307/PC97307 register. Undefined results will occur if a GPIO is configured in this way. TABLE 8-1. The GPIO Registers, Bank 0 Hard Reset Detailed Description ...
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General Purpose Input and Output (GPIO) Ports (Logical Device 7) and Chip Select Output Signals GPIO Register Offset Type Port 1 Lock 00h R/W Register Reserved 01h-07h - 8.2 PROGRAMMABLE CHIP SELECT OUTPUT SIGNALS The part has three programmable chip ...
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Power Management (Logical Device 8) 9.1 POWER MANAGEMENT OPTIONS The power management logical device provides configura- tion options and control of the WATCHDOG feature. 9.1.1 Configuration Options Registers in this logical device enable activation of other logical devices, and ...
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Power Management Data Register, Base Address + 01h This read/write register contains the data in the register pointed to by the Power Management Index register at the base address. See Figure 9- ...
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Bits 6-3 - Reserved Reserved. Bit 7 - GPIO Ports Function Enable 0 - GPIO Ports 1 and 2 are inactive (disabled). Reads and writes are ignored; registers and pins are maintained. Bit 0 of the Activate register (index 30h) ...
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Power Management Control 3 Register (PMC3), Index 04h Hardware resets this register to 0Eh Power Management Reset Required Reserved Parallel Port Clock Enable ...
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Upon reset and upon activation of the power management device, all trigger events are disabled, i.e., bits are cleared to zero. See “The WATCHDOG Feature” on page 172 for more in- formation. WATCHDOG Configuration ...
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POWER MANAGEMENT REGISTER BITMAPS Power Management Reset Required Index of a Power Management Register Read Only 7 6 ...
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WATCHDOG Configuration Reset Required KBD IRQ Mouse IRQ UART 1 IRQ UART 2 IRQ Reserved ...
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... FUNCTIONAL OVERVIEW The X-Bus Data Buffer (XDB) connects the 8-bit X data bus to the system data bus via the data bus of the PC87307/PC97307. The XDB is selected by bit 4 of Super/O Chip Configuration 1 register (index 21h), as described in Section 2.4.3 on page 34. This bit is initialized according to the CFG1 strap pin value ...
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The Internal Clock 11.1 THE CLOCK SOURCE The source of the internal clock of the part can be 24 MHz or 48 MHz clock signals via the X1 pin internal on- chip clock multiplier fed by the ...
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Interrupt and DMA Mapping The standard Plug and Play Configuration registers map IRQs and DMA channels for the part. See Tables 2-8 and 2-9 starting on page 29. 12.1 IRQ MAPPING The part allows connection of some logical devices ...
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Device Description 13.1 GENERAL DC ELECTRICAL CHARACTERISTICS 13.1.1 Recommended Operating Conditions TABLE 13-1. Recommended Operating Conditions Symbol Parameter V V Supply Voltage DD, CCH V Battery Backup Supply Voltage BAT T Operating Temperature A 13.1.2 Absolute Maximum Ratings Absolute ...
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Power Consumption Under Recommended Operating Conditions Symbol Parameter I V Average Main Supply Current Quiescent Main Supply Current in Low Power DD I CCSB Mode V RTC/APC (Logical Device 2) Help Supply CCH I CCH Current ...
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Group 2 Pin List: BUSY, PE, SLCT, WAIT Output from SLCT, PE and BUSY is open-drain in all SPP modes, except in SPP Compatible mode when the setup mode is ECP-based FIFO and bit 4 of the Control2 parallel ...
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Group 5 Pin List: BADDR1,0, CFG3-0 These are CMOS input pins. TABLE 13-9. DC Characteristics of Group 5 Pins Symbol Parameter V Input High Voltage IH V Input Low Voltage IL I Input Leakage Current IL a. Not tested. ...
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Group 8 Pin List: D7-0 TABLE 13-12. DC Characteristics of Group 8 Input Pins Symbol Parameter V Input High Voltage IH V Input Low Voltage IL V Hysteresis H a. Not tested. Guaranteed by design. TABLE 13-13. DC Characteristics ...
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Group 10 Pin List: GPIO27-10, XD5-2, WDO GPIO27-10 are back-drive protected. TABLE 13-16. DC Characteristics of Group 10 Input Pins Symbol Parameter V Input High Voltage IH V Input Low Voltage IL V Hysteresis H I Input Leakage Current ...
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Group 12 Pin List: P12, P16, P17, P20, P21. TABLE 13-20. DC Characteristics of Group 12 Input Pins Symbol Parameter V Input High Voltage IH V Input Low Voltage IL V Hysteresis H a. Not tested. Guaranteed by design. ...
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Group 14 Pin List: PD7-0 Group 14 pins are back-drive protected. TABLE 13-24. DC Characteristics of Group 14 Input Pins Symbol Parameter V Input High Voltage IH V Input Low Voltage IL V Hysteresis H a. Not tested. Guaranteed ...
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Group 17 Pin List: BOUT2,1, DTR2,1, IRSL2-0, RTS2,1, SOUT2,1. TABLE 13-28. DC Characteristics of Group 17 Output Pins Symbol Parameter V Output High Voltage OH V Output Low Voltage OL V Hysteresis H 13.2.18 Group 18 Pin List: DRQ3-0 ...
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Group 22 Pin List: IOCHRDY, ZWS TABLE 13-33. DC Characteristics of Group 22 Output Pins Symbol Parameter V Output High Voltage OH V Output Low Voltage OL 13.2.23 Group 23 Pin List: ONCTL This pin is back-drive protected and ...
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Clock Timing Symbol t Clock High Pulse Width CH t Clock Low Pulse Width Clock Period CP t Internal Clock Period (See Table 13-36.) ICP t Data Rate Period (See Table 13-36.) DRP a. Not tested. ...
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Microprocessor Interface Timing TABLE 13-37. Microprocessor Interface Timing Symbol t Valid Address to Read Active AR t Valid Address to Write Active AW t Data Hold DH t Data Setup DS t Read to Floating Data Bus HZ t ...
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AEN A15-0, DACK RD WR D7-0 PD7-0, ERR, PE, SLCT, ACK, BUSY, GPIO17-10, GPIO27-20 FDC IRQ AEN A15-0, DACK WR RD D7-0 SLIN, INIT, STB, PD7-0, AFD FDC IRQ www.national.com Device Description Valid ...
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AEN or CS A15 D7-0 (Input) FIGURE 13-5. Read After Write Operation to All Registers and RAM 13.3.4 Baud Output Timing Symbol Parameter N Baud Divisor t Baud Output Positive Edge Delay BHD t Baud Output Negative Edge ...
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Transmitter Timing Symbol t a IRTX Pulse Width IRTXW t Delay from WR (WR THR) to Reset IRQ HR t Delay from RD (RD IIR) to Reset IRQ (THRE Delay from Initial IRQ Reset to Transmit Start ...
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Receiver Timing Symbol Parameter t a IRRX Pulse Width IRRXW t Delay from Active Edge Reset IRQ RAI1 t Delay from Active Edge Reset IRQ RAI2 t Delay from Active Edge of RD ...
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SIN Data (5-8) Sample Clock Trigger Level Interrupt LSI Interrupt RD (RD LSR) RD (RD RBR) Note: If SCR0 = 1, then RCLKs. For a time-out interrupt, t SINT SIN Sample Clock Time-Out or Trigger Level Interrupt ...
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UART, Sharp-IR and Consumer-IR Timing TABLE 13-41. UART, Sharp-IR and Consumer Remote Control Timing Symbol Parameter t Single Bit Time in UART and Sharp-IR BT Modulation Signal Pulse Width in Sharp-IR and t CMW Consumer Remote Control Modulation Signal ...
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SIR Timing Symbol Parameter t SIR Signal Pulse Width SPW S SIR Transmitter Data Rate Tolerance DRT t SIR Receiver Edge Jitter Nominal Bit Duration SJT is the nominal bit time in UART, Sharp-IR, SIR and Consumer ...