PC87306 National Semiconductor, PC87306 Datasheet
PC87306
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PC87306 Summary of contents
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... Printed circuit board space savings fewer components on the motherboard and com- patibility with the latest industry standard peripherals are only a few of the benefits of using a PC87306 The KBC is fully software compatible with the 8042AH mi- crocontroller It contains system timing control logic cus- ...
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... SPP EPP (Enhanced Parallel Port) and ECP (Extended Ca- pabilities Port) modes are supported by the parallel port All IDE control signals with DMA support including support for Type F DMA are provided by the PC87306 Only external signal buffers are required to implement a complete IDE interface ...
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PIN DESCRIPTION 2 0 CONFIGURATION REGISTERS 2 1 Overview 2 2 Software Configuration 2 3 Hardware Configuration 2 4 Index and Data Registers 2 5 Base Configuration Registers Function Enable Register Function ...
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... Configuration Registers Access 8 12 Interrupt Generation 9 0 INTEGRATED DEVICE ELECTRONICS INTERFACE (IDE Introduction 9 2 IDE Signals 10 0 KEYBOARD CONTROLLER AND REAL-TIME CLOCK 10 1 PC87306 KBC Function Host System Interface Program Memory Data Memory and Registers Interface Timer Counter (Continued KEYBOARD CONTROLLER AND REAL-TIME ...
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... FIGURE 4-2 IBM Perpendicular and ISO Formats Supported by the Format Command FIGURE 5-1 FDC Data Separator Block Diagram FIGURE 5-2 PC87306 Dynamic Window Margin Performance FIGURE 5-3 Read Data Algorithm State Diagram FIGURE 5-4 Perpendicular Recording Drive R W Head and Pre-Erase Head ...
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FIGURE 12-15 Read Data Timing FIGURE 12-16 Drive Control Timing FIGURE 12-17 IDE Timing FIGURE 12-18 Compatible Mode Parallel Port Interrupt Timing FIGURE 12-19 Extended Mode Parallel Port Interrupt Timing FIGURE 12-20 Typical Parallel Port Data Exchange FIGURE 12-21 Enhanced ...
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... PC87306 UART TABLE 6-2 PC87306 Register Summary for an Individual UART Channel TABLE 6-3 PC87306 UART Reset Configuration TABLE 6-4 PC87306 UART Divisors Baud Rates and Clock Frequencies TABLE 6-5 PC87306 Interrupt Control Functions TABLE 8-1 Parallel Interface TABLE 8-2 Standard Parallel Port ...
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Basic Configuration 12379 – 2 ...
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... Connection Diagram Note Do not connect pins marked Reserved Plastic Quad Flatpak Order Number PC87306VUL See NS Package Number VUL160A 12379 – 3 ...
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... It has a nominal 25 k for further information ) CFG0 1 84 106 I Configuration on Power-Up These CMOS inputs select default configurations in which the PC87306 powers-up (see Table 2-1) They are provided with CMOS input buffers An internal pull-down resistor these pins to V CS0 Programmable Chip Select CS0 1 are programmable chip select and or latch enable and ...
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Pin Description (Continued) TABLE 1-1 Pin Descriptions (Alphabetical) (Continued) Symbol Pin I O DIR 69 O FDC Direction This output determines the direction of the floppy disk drive (FDD) head movement (active DIR is inactive DR0 1 73 ...
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Pin Description (Continued) TABLE 1-1 Pin Descriptions (Alphabetical) (Continued) Symbol Pin I O HDSEL 62 O FDC Head Select This output determines which side of the FDD is accessed When Active the head selects side 1 When inactive ...
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Pin Description (Continued) TABLE 1-1 Pin Descriptions (Alphabetical) (Continued) Symbol Pin I O IRQ8 13 O Interrupt 8 Real-Time Clock interrupt request output This is an open-drain output IRQ12 Interrupt 12 KBC’s mouse interrupt generated ...
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Pin Description (Continued) TABLE 1-1 Pin Descriptions (Alphabetical) (Continued) Symbol Pin I O SIN1 2 110 102 I Serial Input This input receives composite serial data from the communications link (e g peripheral device MODEM or data set) ...
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Pin Description (Continued) TABLE 1-1 Pin Descriptions (Alphabetical) (Continued) Symbol Pin I O X2C 9 O Crystal2 Slow Output for the internal Real-Time Clock crystal oscillator amplifier ZWS 24 O Zero Wait State This pin is the Zero ...
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... Configuration Registers 2 1 OVERVIEW Eighteen registers constitute the Base Configuration Regis- ter set and control the PC87306 setup In general these registers control the enabling of major functions (FDC UARTs parallel port pin functionalty etc ) the I O address these functions and whether they power-down via ...
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... Configuration Registers FIGURE 2-1 PC87306 Configuration Registers (Continued 12379 – 12379 – 12379 – 12379 – 12379 – 12379 – 12379 – 12379 – 12379 – 12379 – 13 ...
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... Configuration Registers FIGURE 2-1 PC87306 Configuration Registers (Continued) (Continued 12379– 12379– 12379– 12379– 12379– 12379 – 12379 – 12379 – 12379 – 12379 – 97 ...
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... Configuration Registers FIGURE 2-1 PC87306 Configuration Registers (Continued HARDWARE CONFIGURATION During reset possible sets of default values are load- ed into the first five Configuration Registers A strapping option on two pins (CFG0 1) selects the set of values that is loaded This allows for automatic configuration without soft- ...
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... FDC is blocked and power- down mode The FDC registers retain all data in pow- er down mode Bit 4 When this bit is zero the PC87306 can control two floppy disk drives directly without an external decod- er When this bit is one the two drive select signals ...
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Configuration Registers TABLE 2-4 Primary and Secondary Drive Address Selection Bit 5 Bit 7 Drive PC-AT Mode 0 X FDC Primary 3F0– FDC Secondary 3F0– IDE Primary 1F0–7 3F6 3F7h X 1 ...
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Configuration Registers TABLE 2-10 TRI-STATE Conditions of IRQ3 and IRQ4 Bit 0 of PNP1 0 Bit 0 of PNP1 e IRQ3 According to FAR (PNP1 bit2 selection and (FER bit1 bits MCR (MCR1 bit3 (MCR1 ...
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Configuration Registers When this bit is 1 Version supported (IEEE 1284) and STB AFD INIT and SLIN are push-pull outputs This bit has the same affect on the output buffers in ECP modes 0 and ...
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... DENSEL’s polarity control bit 0 DENSEL is active low for 500 kbps or 1 Mbps data rates 1 DENSEL is active high for 500 kbps or 1 Mbps data rates System Operation Mode The PC87306 can be Bit 7 configured to either PC- modes mode 1 PC-AT mode Upon reset this bit is initialized to 1 thus select- ...
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... DMA channel number as reflected in the CNFGB register to the selected channel (for the given wiring of those pins to the host DMA channel pins match the value written in bits 2–1 to the value of bit 3 according to the PC87306 wiring Bits 4 5 Reserved Bits 6 7 ...
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Configuration Registers A15 A10 LPTBA When bit 6 of PNP0 is 0 this register is read only and is forced to EFh This register may be modified only when the parallel port is disabled Bit ...
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Configuration Registers 3 Clear PTR bit 1 and then set PTR bit 0 (power-down) high See Section PTR bits 0 and POWER-UP PROCEDURE AND CONSIDERATIONS UART Power-Up The clock ...
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FDC Register Description The FDC has internal 24 mA data bus buffers which allow direct connection to the system bus The internal 40 mA totem-pole disk interface buffers are compatible with both CMOS drive inputs and 150 resistor ...
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FDC Register Description D3 DMA Enable This bit has two modes of operation PC-AT mode Writing this bit enables the FDRQ FDACK TC and IRQ6 pins Writing this bit disables the FDACK ...
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FDC Register Description D5 Valid Data Automatic Media Sense mode The state of bit 5 is determined by the state of the VLD0 1 bits in the ASC Configuration Register If this bit is 0 there is valid ...
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FDC Register Description Data Rate Select Register (DSR) This write-only register is used to program the data rate amount of write precompensation power-down mode and software reset The data rate is programmed via the CCR ...
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FDC Register Description Data Register (FIFO DESC Data 7 0 RESET Byte Mode COND During the Execution Phase of a command involving data transfer to from the FIFO the system must respond ...
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FDC Register Description Status Register 0 (ST0 DESC HDS RESET COND D7 6 Interrupt Code 00 Normal Termination ...
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FDC Register Description D0 Missing Address Mark in Data Field Controller cannot find the Data Field AM during a Read Scan or Verify command Bit 0 of ST1 is also set Status Register 3 (ST3) ...
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FDC Command Set Description The sixth byte of the result phase varies depending on what commands have been previously executed If a format com- mand has previously been issued and no reads or writes have been issued since ...
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FDC Command Set Description TABLE 4-1 Typical Format GAP3 Length Values Based on Drive Data Rate Sector Mode Size (Decimal) 250 kbps 256 MFM 256 512 512 1024 2048 4096 500 kbps 256 MFM 512 512 1024 2048 ...
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FDC Command Set Description Notes A1 Data Pattern of A1 Clock Pattern Data Pattern of C2 Clock Pattern All byte counts in decimal All byte values in hex FIGURE 4-2 IBM ...
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FDC Command Set Description Command Phase TMR IAF IPS 0 LOW PWR FWR FRD BST R255 0 0 DENSEL BFR WLD Head Settle Execution Phase Internal ...
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... The NSC command can be used to distinguish between the FDC versions and the 82077 The Result Phase byte uniquely identifies the floppy controller as a PC87306 which returns a value of 73h The 82077 and DP8473 return a value of 80h signifying an invalid command The lower four ...
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FDC Command Set Description TABLE 4-6 Effect of Drive Mode and Data Rate on Format and Write Commands Data Rate 250 kbps 300 kbps 500 kbps 1 Mbps TABLE 4-7 Effect of GAP and WG on Format and ...
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FDC Command Set Description TABLE 4-8 Sector Size Selection Bytes per Number of Bytes Sector Code in Data Field 0 128 1 256 2 512 3 1024 4 2048 5 4096 6 8192 7 16384 The controller then ...
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FDC Command Set Description TABLE 4-9 SK Effect on the Read Data Command SK Data Type 0 Normal 0 Deleted 1 Normal 1 Deleted TABLE 4-10 Result Phase Termination Values with No Error Last MT HD Sector 0 ...
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FDC Command Set Description The controller first simulates the Motor On time for the se- lected drive internally The user must turn on the drive motor directly by enabling the appropriate drive and motor select disk interface outputs ...
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FDC Command Set Description After the last command byte is issued the DRx BUSY bit is set in the MSR for the selected drive The controller will simulate the Motor On time and then enter the Idle Phase ...
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FDC Command Set Description SCAN EQUAL Command Phase MT MFM IPS Track Number Drive Head Number Sector Number Bytes per Sector End of Track Sector Number Intersector Gap Length ...
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FDC Command Set Description Command Phase New Track Number MSN of Track Number 0 0 Note The last Command Phase byte is required only if ETR ...
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FDC Command Set Description TABLE 4-15 Set Track Register Address DS1 DS0 MSB Register Addressed PTR0 (LSB PTR0 (MSB PTR1 (LSB PTR1 (MSB ...
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FDC Command Set Description The Motor Off and Motor On timers are artifacts of the NEC PD765 These timers determine both the delay from se- lecting a drive motor until a read or write operation is start- ed ...
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FDC Command Set Description Version Command The Version command can be used to determine the floppy controller being used The Result Phase uniquely identifies the floppy controller version The FDC returns a value of 90h ...
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FDC Command Set Description Result Phase Status Register 0 Status Register 1 Status Register 2 Track Number Head Number Sector Number Bytes per Sector 4 2 COMMAND SET SUMMARY CONFIGURE Command Phase ...
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FDC Command Set Description READ DATA Command Phase MT MFM IPS Track Number Drive Head Number Sector Number Bytes per Sector End of Track Sector Number Intersector Gap Length ...
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FDC Command Set Description Execution Phase Disk drive head stepped in or out a pro- grammable number of tracks Result Phase None SCAN EQUAL Command Phase MT MFM IPS ...
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FDC Command Set Description SENSE DRIVE STATUS Command Phase Execution Phase Disk drive status information is detected and reported Result Phase Status Register 3 SENSE INTERRUPT ...
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FDC Command Set Description Execution Phase Data is transferred from the system to the controller via DMA or Non-DMA modes and written to the disk Result Phase Status Register 0 Status Register 1 Status Register 2 Track Number ...
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FDC Command Set Description 4 3 MNEMONIC DEFINITIONS FOR FDC COMMANDS Symbol Description BFR Buffer enable bit used in the Mode command Enabled open-collector output buffers BST Burst Mode disable control bit used in Mode command Selects the ...
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... FDC Functional Description The PC87306 is software compatible with the DP8473 and 82077 floppy disk controllers Upon a power on reset the 16-byte FIFO will be disabled Also the disk interface out- puts will be configured as active push-pull outputs which are compatible with both CMOS inputs and open-collector ...
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FDC Functional Description software polling mode The last two modes are called the Non-DMA modes The DMA mode is used if the system has a DMA controller This allows the other tasks while the data ...
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FDC Functional Description DACK asserted alone without strobe is also counted as a transfer are not being strobed for each byte DACK must be strobed for each byte so that ...
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FDC Functional Description FIGURE 5-1 FDC Data Separator Block Diagram If a new command is issued when the FDC is in the middle of a polling routine the MSR will not indicate a ready status for the next ...
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... FDC Functional Description 250 kbps 500 kbps FIGURE 5-2 PC87306 Dynamic Window Margin Performance (Typical performance at V window margin (or bit jitter) that the data separator can han- dle with no read errors Thus the area under the dynamic window margin curves in Figure 5-2 is the range of MSV and ...
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FDC Functional Description The 2 88M drive has unique format and write data timing requirements due to its read write head and pre-erase head design (see Figure 5-4 ) Unlike conventional disk drives which have only a read ...
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... They will remain active the user to ensure that the Motor and Drive Select signals are turned off Note If the power to an external oscillator driving the PC87306 independently removed during the FDC low power mode it must not be done until 2 ms after the FDC low power command is issued ...
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... SERIAL PORT REGISTERS Two identical register sets one for each channel are in the PC87306 All register descriptions in this section apply to the register sets in both channels See Table 6-1 TABLE 6-1 PC87306 UART Register Addresses (AEN ...
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... Serial Ports (Continued) TABLE 6-2 PC87306 Register Summary for an Individual UART Channel A0 – –2 0 A0– DLAB 0 DLAB 0 DLAB Receiver Transmitter Interrupt Bit Interrupt Buffer Holding Ident No Enable Register Register Register Register (Read (Write (Read Only) Only) Only) RBR THR ...
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... Serial Ports (Continued) TABLE 6-3 PC87306 UART Reset Configuration Register or Signal Interrupt Enable Master Reset (MR) Interrupt Identification Master Reset FIFO Control Master Reset Line Control Master Reset MODEM Control Master Reset Line Status Master Reset MODEM Status Master Reset SOUT ...
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Serial Ports (Continued LINE STATUS REGISTER (LSR) This 8-bit register provides status information to the CPU concerning the data transfer Table 6-2 shows the contents of the Line Status Register Details on each bit follow Bit ...
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Serial Ports (Continued) FCR Bits RCVR FIFO Trigger Level (Bytes FIGURE 6-2 Receiver FIFO Trigger Level 6 6 INTERRUPT IDENTIFICATION REGISTER (IIR) In order ...
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... An IR interface connects a UART’s serial in and serial out signals via one or more transmitter LED and receiver photo diode pairs The IR port of the PC87306 is hooked to UART2 SOUT of UART2 is also encoded by the PC87306 and routed to the InfraRed Transmitter (IRTX) pin The InfraRed Receiver pin ...
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... IRTX and IRRX are controlled by the UART2 TRI- STATE control bit (bit 3 of SCF0) The outputs are in TRI- STATE and the inputs are blocked to reduce the leakage current when the UART2 TRI-STATE control bit is 1 and either UART2 is disabled or the PC87306 is in power-down mode 12379 – 38 ...
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... TRI-STATE Special circuitry provides protection against damage that might be caused when the printer is powered but the PC87306 is not There are two Standard Parallel Port (SPP) modes of opera- tion (Compatible and Extended see Table 8-2) two En- hanced Parallel Port (EPP) modes of operation and one Ex- ...
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Parallel Port (Continued) Bit 0 When in EPP mode this is the timeout status bit When this bit timeout When this bit is 1 timeout occurred on EPP cycle (minimum cleared ...
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Parallel Port (Continued Address Register Data (DTR Status (STR Control (CTR Address Data Port 0 ...
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Parallel Port (Continued WAIT is low during the host read cycle then the EPP pulls IOCHRDY low When WAIT goes high the EPP stops pulling IOCHRDY to low 4 When IOCHRDY goes high it causes RD ...
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Parallel Port (Continued) FIGURE 8-4 EPP 1 9 Address Write EPP 1 9 Address Read The following procedure reads from the address register See also Figure 8-5 1 The host reads a byte from the EPP address register ...
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Parallel Port (Continued EXTENDED CAPABILITIES PARALLEL PORT (ECP Introduction The ECP support includes a 16-byte FIFO that can be con- figured for either direction command data FIFO tags (one per byte) a FIFO ...
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Parallel Port (Continued Software Operation Software operation is detailed in the document Extended Capabilities Port Protocol and ISA Interface Standard To highlight the ECP usage some software operations are de- tailed below 1 The software ...
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Parallel Port (Continued) The FIFO does not stall when overwritten or underrun (ac- cess is ignored) Bytes are always read from the top of the FIFO regardless of the direction bit (bit 5 of DCR) For ex- ample ...
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Parallel Port (Continued SOFTWARE CONTROLLED DATA TRANSFER (Modes 000 and 001) Software controlled data transfer is supported in modes 000 and 001 The software generates peripheral-device cycles by modifying the DATAR and DCR registers and reading ...
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... Changed register on the floppy disk controller at that ad- dress) The two ’LS245 chips are used to enable or TRI-STATE the data bus signals In the PC-AT mode the PC87306 provides the two hard disk chip selects (HCS0 HCS1) for the IDE interface The HCS0 output is active low when the 1F0– 1F7h I O ...
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... Integrated Device Electronics Interface (IDE) The IDE Interface Circuit has some additional IDE DMA sup- port When bit 1 of FCR is 1 the PC87306 IDE responds to a DMA acknowledgement on the IDEACK input pin as fol- lows a) IDEL0 is asserted when IDEACK is asserted and either ...
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... The KBC is enabled when bit 0 of KRR guaranteed to work with SYSCLK MHz (when KRR7 The KBC is software compatible with the 8042AH industry standard keyboard controller as well as National’s PC87911 The PC87306 can execute code previously writ- ten for an 8042 without further development 12379 – ...
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... Data bus D0 –D7 connects to the peripheral bus XD0–XD7 of the system The IOR and IOW inputs connect to the IOR and IOW lines of the system All read and write operations to the PC87306 are I O operations The PC87306 decodes the keyboard controller chip-select from A0 – ...
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... NOTE EN FLAGS command (used for routing OBF and IBF onto P24 and P25) will cause unpredictable results and should not be issued Program Memory The keyboard controller of the PC87306 has ROM based program memory An 11-bit program counter allows direct access to every location of the program memory Fig- ...
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... RETR Return instruction is executed PSW is restored PSW is not restored if an RET Return instruction is executed See Figure 10 Interface The keyboard controller of the PC87306 provides 16 gener- al purpose I O lines two open-collector output lines and two input lines as shown in the Functional Block Diagram in Figure 10-1 General Purpose I O The 16 general purpose I O lines P12– ...
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... Timer Overflow Flag and Timer inter- rupt operate in the same way as they do in the timer mode Interrupts The keyboard controller of the PC87306 provides 2 different internal interrupts They are the Input Buffer Full (IBF) inter- rupt and Timer Overflow interrupt These two interrupts can ...
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... FIGURE 10-12 Instruction Cycle Timing (Continued REAL-TIME CLOCK FUNCTION The RTC in the PC87306 is a low-power clock that provides a time-of-day clock and 100-year calendar with alarm fea- tures and battery operation Other features include three maskable interrupt sources and 242 bytes of general pur- ...
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... Also writes to time registers during an update have undefined results To avoid accessing invalid data the RTC in the PC87306 provides a user copy of the time registers The sequence used to update the time registers is shown in Figure 10-14 Four methods are available for reading and writing time to ...
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... Power Management The Power Management function provides power to the RTC in the PC87306 During system operation power from the system is used When system voltage falls below battery voltage the Power Management function switches the RTC cell to battery power For proper operation a 500 mV differ- ...
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... Oscillator When power is applied to the RTC in the PC87306 the Oscillator is operational with the following exceptions 1 The VRT bit (bit 7 in Control Register The oscillator is disabled after initial power-up This reduces ...
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Keyboard Controller and Real-Time Clock Control Register B SET PIE AIE UIE 0 DM bit Bit 0 DSE Daylight Savings Enable (Read Write) 1 Enables daylight savings Two conditions ap- ply as ...
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... General Purpose Input and Output (GPIO) Ports The PC87306 supports two identical General Purpose I O (GPIO) ports See Figure 11-1 The PC87306 can wake up with both GPIO Ports either en- abled or disabled according to the CFG1 strap pin GPIO Port offset 0 and GPIO Port offset 1 from the 16-bit GPIO Port base address The GPIO port’ ...
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... Electrical Characteristics ABSOLUTE MAXIMUM RATINGS (Notes 1 and 2) If Military Aerospace specified devices are required please contact the National Semiconductor Sales Office Distributors for availability and specifications Supply Voltage ( Input Voltage ( Output Voltage ( Storage Temperature ( STG Power Dissipation ( Lead Temperature ( (Soldering 10 seconds) ...
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... High Level Output Current (Note Low Level Output Current OL Note 1 AFD INIT SLIN and STB are open drain pins when the PC87306 parallel port is operating in one of the following modes Compatible Extended EPP1 7 ECP mode ECP mode 2 if PCR1 GPIO Pins Symbol ...
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Electrical Characteristics Keyboard Controller and Real-Time Clock Pins 0 C–70 C Symbol Parameter V Minimum High Level Output Voltage OH P10–P17 P20–P27 (Note 1) All other push-pull outputs KBCLK KBDAT MCLK MDAT (Note 2) V ...
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Electrical Characteristics Clock Timing Symbol Parameter t Clock High Pulse Width CH t Clock Low Pulse Width CL t Clock Period CP t Internal Clock Period ICP t Data Rate Period DRP TABLE 12-1 Nominal ...
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Electrical Characteristics FIGURE 12-2 Microprocessor Read Timing FIGURE 12-3 Microprocessor Write Timing FIGURE 12-4 Read after Write Operation to All Registers and RAM Timing (Continued 12379 – 12379 – ...
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Electrical Characteristics Baud Out Timing Symbol Parameter N Baud Divisor t Baud Output Positive Edge Delay BHD t Baud Output Negative Edge Delay BLD Transmitter Timing Symbol Parameter t IRTX Pulse Width ...
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Electrical Characteristics Receiver Timing Symbol Parameter t IRRX Pulse Width IRRXW t Delay from Active Edge Reset IRQ RAI t Delay from Inactive Edge of RD (RD LSR) to Reset IRQ RINT ...
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Electrical Characteristics Note 1 If SCR0 1 then t 3 RCLKs For a Timeout Interrupt SINT FIGURE 12-9 Timeout Receiver Timing MODEM Control Timing Symbol Parameter t Delay from WR (WR MCR) ...
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Electrical Characteristics DMA Timing FDC Symbol Parameter t FDACK Inactive Pulse Width KI t FDACK Active Pulse Width KK t FDACK Active Edge to FDRQ Inactive KQ t FDRQ to FDACK ...
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Electrical Characteristics ECP Symbol Parameter t PDACK Inactive Pulse Width KIP t PDACK Active Pulse Width KKP t PDACK Active Edge to PDRQ Inactive (Notes 2 3) KQP t PDRQ to PDACK Active Edge ...
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Electrical Characteristics Reset Timing Symbol Parameter t Reset Width (Note Reset to Control Inactive SRC Note 1 The software reset pulse width is 100 ns Note 2 DRQ and IRQ6 will be ...
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Electrical Characteristics FDC Read Data Timing Symbol Parameter t Read Data Pulse Width RDW Drive Control Timing Symbol Parameter t DR0– 3 MTR0–3 from End of WR DRV t DIR Setup to ...
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Electrical Characteristics Parallel Port Timing Symbol Parameter t Port Data Hold PDH t Port Data Setup PDS t Port Interrupt PI t STB Width SW Note 1 These times are system dependent and are therefore ...
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... EPP 1 9 only if WAIT is low when WR becomes active else t WST WW Note 2 The PC87306 design guarantees that WRITE will not change from low to high before DSTRB or ASTRB goes from low to high Note 3 In EPP 1 9 IOCHRDY inactive is measured from FIGURE 12-21 Enhanced Parallel Port Timing ...
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Electrical Characteristics Extended Capabilities Port Timing Forward Symbol Parameter t Data Setup before STB Active ecdsf t Data Hold after BUSY ecdhf t BUSY Setup after STB Active eclhf t STB ...
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Electrical Characteristics GPIO Write Timing Symbol Parameter t Write data to GPIO update WGO Note 1 GPIO are open drain pins with 10 k external pull-ups Note Refer to Microprocessor Interface Timing for Read Timing ...
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Electrical Characteristics Programmable Chip Select Timing Symbol Parameter t Delay from Command to Enable Chip Select CE t Delay from Command to Disable Chip Select CD (Continued) Min 0 0 FIGURE 12-27 Chip Select Timing ...
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109 ...
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... National does not assume any responsibility for use of any circuitry described no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications Plastic Quad Flatpak Order Number PC87306VUL NS Package Number VUL160A 2 A critical component is any component of a life ...