CY7C024V-25AC Cypress Semiconductor Corporation., CY7C024V-25AC Datasheet
CY7C024V-25AC
Specifications of CY7C024V-25AC
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CY7C024V-25AC Summary of contents
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... Features • True dual-ported memory cells which allow simulta- neous access of the same memory location • 4/8/16K x 16 organization (CY7C024V/025V/026V) • 4/ organization (CY7C0241V/0251V) • 16K x 18 organization (CY7C036V) • 0.35-micron CMOS for optimum speed/power [1] • High-speed access: 15 /20/25 ns • Low operating power — ...
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... Control of a semaphore indicates that a shared resource is in use. An automatic power-down feature is controlled inde- pendently on each port by a chip select (CE) pin. The CY7C024V/025V/026V and CY7C0241V/0251V/036V are available in 100-pin Thin Quad Plastic Flatpacks (TQFP). 100-Pin TQFP Top View CY7C024V (4K x 16) CY7C025V ( CY7C024V/025V/026V CY7C0241V/0251V/036V 75 NC ...
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... I/O2R 16 VCC 17 I/O3R 18 I/O4R 19 I/O5R 20 I/O6R Notes the CY7C0251. 12L the CY7C0251. 12R PRELIMINARY Top View 100-Pin TQFP CY7C0241V (4K x 18) CY7C0251V ( CY7C026V (16K x 16 CY7C024V/025V/026V CY7C0241V/0251V/036V INT L 65 BUSY 64 L GND 63 M/S 62 BUSY 61 R INT A6L 71 A5L 70 A4L 69 A3L 68 A2L 67 ...
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... CMOS Level) Shaded areas contain advance information. PRELIMINARY 100-Pin TQFP Top View 100 CY7C036V (16K x 18 CY7C024V/025V/026V CY7C024V/025V/026V CY7C0241V/0251V/036V CY7C0241V/0251V/036V [1] -15 15 125 CY7C024V/025V/026V CY7C0241V/0251V/036V 13L INT L 65 BUSY 64 L GND 63 M/S 62 BUSY 61 R INT 13R CY7C024V/025V/026V CY7C0241V/0251V/036V -20 - 120 115 ...
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... Output Current into Outputs (LOW)............................. 20 mA Static Discharge Voltage .......................................... >2001V Latch-Up Current .................................................... >200 mA Operating Range Range Commercial Industrial +0.5V CC Shaded areas contain advance information. +0. CY7C024V/025V/026V CY7C0241V/0251V/036V Description –A for 8K devices; A –A for 16K for x16 devices; I/O –I/O for x18 devices) ...
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... MAX Indust. Test Conditions MHz 3. 250 TH OUTPUT C = 30pF V TH (b) Thévenin Equivalent (Load 1) ALL INPUT PULSES 3.0V 90% 90% 10% 10% GND CY7C024V/025V/026V CY7C0241V/0251V/036V -20 -25 2.4 2.4 0.4 0.4 2.0 2.0 0.8 0.8 –10 10 –10 10 –10 10 –10 10 120 175 115 165 140 195 ...
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... This parameter is guaranteed but not tested. For information on port-to-port delay through RAM cells from writing port to reading port, refer to Read Timing with Busy waveform. 18. For information on port-to-port delay through RAM cells from writing port to reading port, refer to Read Timing with Busy waveform. PRELIMINARY [13] CY7C024V/025V/026V CY7C0241V/0251V/036V [1] -15 Min. Max less than t and t HZCE LZCE 7 CY7C024V/025V/026V CY7C0241V/0251V/036V -20 -25 Min. Max. Min. Max ...
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... SEM Address Access Time SAA Data Retention Mode The CY7C024V/025V/026V and CY7C0241V/0251V/036V are designed with battery backup in mind. Data retention volt- age and supply current are guaranteed over temperature. The following rules ensure data retention: 1. Chip Enable (CE) must be held HIGH during data retention, with- ...
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... Address valid prior to or coincident with CE transition LOW. 26. To access RAM SEM = PRELIMINARY [22, 23, 24 [22, 25, 26] t ACE t DOE t LZOE t LZCE LZCE t ABE t ACE t LZCE . This waveform cannot be used for semaphore reads access semaphore SEM = CY7C024V/025V/026V CY7C0241V/0251V/036V t OHA DATA VALID t HZCE t HZOE DATA VALID OHA t HZCE t HZCE ...
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... If the CE or SEM LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the high-impedance state. PRELIMINARY [27, 28, 29, 30 [30] t PWE [33] t HZWE t SD [27, 28, 29, 35 SCE LOW CE or SEM and a LOW PWE HZWE . CY7C024V/025V/026V CY7C0241V/0251V/036V [33] t HZOE LZWE NOTE allow the I/O drivers to turn off and data to be placed PWE ...
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... SPS PRELIMINARY [36 SCE SOP t SD DATA VALID PWE t SWRD t SOP WRITE CYCLE READ CYCLE [37, 38, 39] MATCH t SPS MATCH = CE = HIGH CY7C024V/025V/026V CY7C0241V/0251V/036V t t SAA OHA VALID ADRESS t ACE DATA VALID OUT t DOE ...
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... Switching Waveforms (continued) Timing Diagram of Read with BUSY (M/S=HIGH) ADDRESS R R/W R DATA ADDRESS L BUSY L DATA OUTL Write Timing with Busy Input (M/S=LOW) R/W BUSY Note: 40 LOW PRELIMINARY [40 MATCH t PWE t SD VALID MATCH t BLA t PWE CY7C024V/025V/026V CY7C0241V/0251V/036V BHA t BDD t DDD VALID t WDD ...
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... Note: 41 violated, the busy signal will be asserted on one side or the other, but there is no guarantee to which side BUSY will be asserted. PS PRELIMINARY [41] ADDRESS MATCH BLC ADDRESS MATCH BLC [41 ADDRESS MISMATCH t t BLA BHA ADDRESS MISMATCH t t BLA BHA 13 CY7C024V/025V/026V CY7C0241V/0251V/036V t BHC t BHC ...
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... INS Left Side Clears INT L : ADDRESS R INT L Notes: 42. t depends on which enable pin ( depends on which enable pin (CE INS INR L PRELIMINARY t WC [42 [43] t INR t WC [42 [43] t INR ) is deasserted first R asserted last CY7C024V/025V/026V CY7C0241V/0251V/036V t RC READ 7FFF (OR 1/3FFF READ 7FFE OR 1/3FFE) ...
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... The upper two memory locations may be used for message passing. The highest memory location (FFF for the CY7C024V/41V, 1FFF for the CY7C025V/51V, 3FFF for the CY7C026V/36V) is the mailbox for the right port and the sec- ond-highest memory location (FFE for the CY7C024V/41V, 1FFE for the CY7C025V/51V, 3FFE for the CY7C026V/36V) is the mailbox for the left port ...
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... Right port has semaphore token 1 1 Semaphore free 0 1 Left port has semaphore token 1 1 Semaphore free 16 CY7C024V/025V/026V CY7C0241V/0251V/036V I/O –I/O Operation 0 8 Deselected: Power-Down Deselected: Power-Down Write to Upper Byte Only Write to Lower Byte Only Write to Both Bytes Read Upper Byte Only ...
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... Ordering Information 4K x16 3.3V Asynchronous Dual-Port SRAM Speed (ns) Ordering Code [1] 15 CY7C024V-15AC 20 CY7C024V-20AC CY7C024V-20AI 25 CY7C024V-25AC CY7C024V-25AI 8K x16 3.3V Asynchronous Dual-Port SRAM Speed (ns) Ordering Code [1] 15 CY7C025V-15AC 20 CY7C025V-20AC CY7C025V-20AI 25 CY7C025V-25AC CY7C025V-25AI 16K x18 3.3V Asynchronous Dual-Port SRAM Speed (ns) Ordering Code [1] 15 CY7C026V-15AC ...
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... Package Type A100 100-Pin Thin Quad Flat Pack A100 100-Pin Thin Quad Flat Pack A100 100-Pin Thin Quad Flat Pack A100 100-Pin Thin Quad Flat Pack A100 100-Pin Thin Quad Flat Pack 18 CY7C024V/025V/026V CY7C0241V/0251V/036V Operating Range Commercial Commercial Industrial Commercial Industrial 51-85048-B ...
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... POR circuit. If the dual-port func- tions properly once the ramp rate is slowed to 100 ns or great- er, then the POR circuit is at fault. Applicable devices—All speed/package/temperature combi- nations of the following: • CY7C024V • CY7C025V • CY7C026V • CY7C0241V • CY7C0251V • ...