TP3410J304 National Semiconductor, TP3410J304 Datasheet
TP3410J304
Specifications of TP3410J304
Available stocks
Related parts for TP3410J304
TP3410J304 Summary of contents
Page 1
... D data is multiplexed together with control spare bits and loop maintenance data on 4 pins Combo and TRI-STATE are registered trademarks of National Semiconductor Corporation MICROWIRE is a trademark of National Semiconductor Corporation TM The General Circuit Interface ( interface specification of the Group-of-Four Euro- ...
Page 2
Connection Diagrams Pin Names for MICROWIRE Mode Top View Pin Descriptions Pin Symbol Description No 24 GNDA Negative power supply pins which must 9 GNDD1 be connected together close to the de- 23 GNDD2 vice All digital signals are referenced ...
Page 3
Pin Descriptions (Continued) PIN DESCRIPTIONS SPECIFIC TO MICROWIRE MODE e ONLY (MW 1) Pin Symbol Description Receive 2B1Q signal differential inputs from the line transformer For normal full- duplex operation these pins should ...
Page 4
Pin Descriptions (Continued) Pin Symbol Description The digital input for multiplexed B D and control data clocked by BCLK at the rate of 1 data bit per 2 BCLK cycles and 32 data bits per 8 kHz ...
Page 5
Functional Description 1 1 Power-On Initialization When power is first applied power-on reset circuitry initializ- es the TP3410 and puts it into the power-down state in which all the internal circuits including the Master oscillator are inactive and in a ...
Page 6
Functional Description (Continued) Framing 1 – 9 Quat Positions 1 – 18 Bit Positions Sync Word Superframe Basic Frame 1 1 ISW ISW ...
Page 7
Functional Description (Continued Line Transmit Section Data to be transmitted to the line consists of the customer’ channel data and the data from the maintenance processor plus other ‘‘spare’’ bits in the overhead chan- nels ...
Page 8
Functional Description (Continued Embedded Operations Channel The EOC channel consists of 2 complete 12-bit messages per superframe distributed through the M1 M2 and M3 bits of each half-superframe as shown in Table I Each message is composed of ...
Page 9
Functional Description (Continued) Format 2 Format 2 is the IDL in which the 2B transfer is assigned to the first 19 bits of the frame on the Bx and Br pins Channels are as- signed as follows B1 (8 bits) ...
Page 10
Functional Description (Continued) Transmit slots are numbered relative to FSa and receive slots relative to FSb Shown with examples of offset frames and Time-slot Assignments FIGURE 3-3 DSI Format 3 (Time-Slot Assignment) Slave Mode FSa defines B1 channel for Tx ...
Page 11
Functional Description (Continued Relationship To Data (Microwire Mode) For applications on a line-card in DSI Slave Mode the B and D channel slots can be interfaced to a Time-Division Multiplexed (TDM) bus and assigned to a time-slot ...
Page 12
Functional Description (Continued) Shown with example of Time-slot Assignment and FS a FIGURE 5 D-Port Interface Timing Using BCLK MICROWIRE CONTROL PORT (MW When Format used control information and maintenance channel ...
Page 13
Functional Description (Continued) The TP3410 has an enhanced MICROWIRE port such that it can connect to standard MICROWIRE master devices (such an NSC’s HPC and COP families) as well as the SCP (serial control port) interface master from the Motorola ...
Page 14
Functional Description (Continued GCI Frame Structure Figure 7 shows the frame structure at the GCI interface One GCI channel supports one TP3410 using a bandwidth of 256 kbit s consisting of the following channels multi- plexed together in ...
Page 15
Functional Description (Continued) Byte 1 (Register Address) Function Operation (NOP Write OPR Readback OPR Write CR1 Readback CR1 Write CR2 0 ...
Page 16
Functional Description (Continued) Byte 1 (Register Address) Function READABLE CONFIGURATION REGISTERS Default (No Change Write Cycle) OPR Contents CR1 Contents CR2 Contents ...
Page 17
Functional Description (Continued COMMAND REGISTER FUNCTIONS All addressing and bit-level functions are the same for both the Microwire and GCI Monitor Channels except where not- ed Register addresses are listed in Table II An asterisk indicates the Power-on ...
Page 18
Functional Description (Continued) a mode and the 2B D slots at the receive digital interface port(s) are in the high impedance state BP1 Not Used This bit is not used and should always be set to zero e BP1 0 ...
Page 19
Functional Description (Continued) RFS Remote Febe Select e RFS 1 (default state) The state of the outgoing bit is computed based on the state of the TFB (bit 1) in TXM56 register The TFB blt is set by the software ...
Page 20
Functional Description (Continued) Byte DR5 DR4 DR3 DR2 DR1 DR0 At Power-On Reset this register is initialized Receive D Channel Time-Slot Assignment Select DR5 – DR0 SR1 – SR0 DR5 ...
Page 21
Functional Description (Continued Transmit M5 M6 Spare Bits Register TXM56 (Write Only) Byte LEC M51 M61 M52 At Power-On Reset and each time the device is Deactivat- ed (or ...
Page 22
Functional Description (Continued) The RXM4 Register consists of 8 bits which correspond to the M4 overhead bit position in each of the 8 Basic Frames of a superframe When the line is fully superframe synchro- nized the device extracts from ...
Page 23
Functional Description (Continued) FA0 This command may be used on a fully activated line to force the transmit ‘‘act’’ bit a loss or denial transparency to the NT (LT state J7) To revert back to sending ‘‘act’’ ...
Page 24
Functional Description (Continued) Deactivation is initiated by writing the DR command in the e Activation Control Register causing ‘‘dea’’ mitted towards the NT When the NT ceases to transmit confirmation of deactivation is provided Status indi- cator ...
Page 25
Applications Information (Continued) Note matching may be required to meet the longitudinal balance specification depending on the Longitudinal impedance to ground of the line interface The 15X and 1k resistors in the line interface circuit should be ...
Page 26
... preliminary and parameter limits are not indicative of characterization data with respect to power supply or temperature varia- tions Please contact your National Semiconductor Sales Office for the most current product information Symbol Parameter DIGITAL INTERFACES V Input Low Voltage ...
Page 27
Timing Characteristics Symbol Parameter FMCK Master Clock Frequency Master Clock Tolerance MCLK XTAL Input Clock Jitter tMH Clock Pulse Width tML Hi Low for MCLK tMR Rise and Fall Time tMF of MCLK DIGITAL INTERFACE ( Figures 11 12 and ...
Page 28
Timing Characteristics (Continued) Symbol Parameter MICROWIRE CONTROL INTERFACE (see Figure 14 ) tCH CCLK High Duration tCL CCLK Low Duration tSIC Setup Time CI Valid to CCLK High tHCI Hold Time CCLK High to CI Invalid tSSC Setup Time from ...
Page 29
Timing Diagrams FIGURE 11 Non-Delayed Data Timing Mode (Formats 1 and 3) FIGURE 12 Delayed Data Timing Mode (Formats 1 2 and 9151 – 28 (Shown with TS0 Selected 9151 – ...
Page 30
Timing Diagrams (Continued) Note output (GCI Master high for 8 bit intervals (16 BCLK cycles input (GCI Slave FIGURE 14a TP3410 Enhanced MICROWIRE Control Port Timing FIGURE 13 GCI and Format ...
Page 31
Timing Diagrams (Continued) FIGURE 14b TP3410 Normal MICROWIRE CLOCK Format FIGURE 14c TP3410 Alternate MICROWIRE CLOCK Format 9151 – 9151 – 30 ...
Page 32
... Floor Straight Block Ocean Centre 5 Canton Rd a 49) 0-180-530 85 85 Tsimshatsui Kowloon Tel ( a 49) 0-180-532 78 32 Hong Kong a 49) 0-180-532 93 58 Tel (852) 2737-1600 Tel ( a 49) 0-180-534 16 80 Fax (852) 2736-9960 National Semiconductor Japan Ltd Tel 81-043-299-2309 Fax 81-043-299-2408 ...