UPD78P014YCW Renesas Electronics Corporation., UPD78P014YCW Datasheet
UPD78P014YCW
Available stocks
Related parts for UPD78P014YCW
UPD78P014YCW Summary of contents
Page 1
User’s Manual PD78014, 78014Y SUBSERIES 8-BIT SINGLE-CHIP MICROCONTROLLERS PD78011B PD78012B PD78013 PD78014 PD78P014 PD78011B (A) PD78012B (A) PD78013 (A) PD78014 (A) Document No. U10085EJ7V0UM00 (7th edition) Date Published October 1997 N © 1992 Printed in Japan PD78011BY PD78012BY PD78013Y PD78014Y ...
Page 2
[MEMO] 2 ...
Page 3
NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation ...
Page 4
FIP, IEBus, and QTOP are trademarks of NEC Corporation. Microsoft and Windows are either registered trademarks or trademarks of Microsoft Corporation in the United States and/or other countries. IBM DOS, PC/AT, and PC DOS are trademarks of International Business Machines ...
Page 5
Caution Purchase of NEC I C components conveys a license under the Philips I these components Specification as defined by Philips. The application circuits and their parameters are for reference only and are not intended for ...
Page 6
Regional Information Some information contained in this document may vary from country to country. Before using any NEC product in your application, please contact the NEC office in your country to obtain a list of authorized representatives and distributors. They ...
Page 7
Pages p. 43, 44, 56, 57 The following subseries were added in sections 1.6 and 2.6, “78K/0 Series Expansion.” PD78075B, 78075BY, 780018, 780018Y, 780058, 780058Y, 780034, 780034Y, 780024, 780024Y, 78014H, 780964, 780924, 780228, 78044H, 78044F, 78098B, 780973 Subseries p. 137 ...
Page 8
[MEMO] 8 ...
Page 9
Readers This manual has been prepared for user engineers who want to understand the functions of the PD78014, 78014Y Subseries and design and develop its application systems and programs. Target subseries are as follows. • PD78014 Subseries : PD78011B, 78012B, ...
Page 10
To confirm the details of the register whose register name is known: Refer to APPENDIX D REGISTER INDEX. For the details of the PD78014, 78014Y Subseries instruction function: Refer to the 78K/0 SERIES USER’S MANUAL, Instructions. (IEU1372). For the electrical ...
Page 11
Chapter composition This manual describes points for which functions of PD78014 and PD78014Y Subseries are not same in different chapters. The chapters explaining the subseries are shown in the table below. If you use one of the subseries, you should ...
Page 12
Differences between PD78014 Subseries and PD78014Y Subseries The PD78014 Subseries and PD78014Y Subseries differ in some of the serial interface channel 0 modes as shown below. Mode of Serial Interface 3-wire serial I/O mode 2-wire serial I/O mode SBI (serial ...
Page 13
Document related to development tools (User’s Manual) Document name RA78K Series Assembler Package RA78K Series Structured Assembler Preprocessor RA78K0 Assembler Package CC78K Series C Compiler CC78K0 C Compiler CC78K/0 C Compiler Application Note CC78K Series Library Source File PG-1500 ...
Page 14
Other related documents Document Name IC Package Manual Semiconductor Device Mounting Technology Manual Quality Grade of NEC Semiconductor Devices Reliability and Quality Control of NEC Semiconductor Devices Electrostatic Discharge (ESD) Test Guide to Quality Assurance of Semiconductor Devices Guide ...
Page 15
CHAPTER 1 OUTLINE ( PD78014 Subseries)......................................................................... 1.1 Features .......................................................................................................................... 1.2 Application Fields .......................................................................................................... 1.3 Ordering Information ..................................................................................................... 1.4 Quality Grade ................................................................................................................. 1.5 Pin Configurations (Top View) ..................................................................................... 1.6 78K/0 Series Expansion ................................................................................................ 1.7 Block Diagram ................................................................................................................ 1.8 Outline of Function ...
Page 16
V ...................................................................................................................................... DD 3.2.15 V ....................................................................................................................................... SS 3.2. PD78P014 only) ....................................................................................................... PP 3.2.17 IC (Mask ROM version only) ............................................................................................. 3.3 Input/Output Circuit and Recommended Connection of Unused Pins .................. CHAPTER 4 PIN FUNCTION ( PD78014Y Subseries) ............................................................ ...
Page 17
Operand Address Addressing ..................................................................................... 115 5.4.1 Data memory addressing ................................................................................................... 115 5.4.2 Implied addressing ............................................................................................................. 120 5.4.3 Register addressing ........................................................................................................... 121 5.4.4 Direct addressing ............................................................................................................... 122 5.4.5 Short direct addressing ...................................................................................................... 123 5.4.6 Special function register (SFR) addressing ...................................................................... ...
Page 18
CHAPTER 8 16-BIT TIMER/EVENT COUNTER ........................................................................ 171 8.1 Outline of On-chip Timer in PD78014, 78014Y Subseries ..................................... 171 8.2 16-Bit Timer/Event Counter Functions ....................................................................... 172 8.3 16-Bit Timer/Event Counter Configuration ................................................................ 173 8.4 16-Bit Timer/Event Counter Control Registers ......................................................... 178 ...
Page 19
Clock Output Function Control Registers ................................................................. 240 CHAPTER 13 BUZZER OUTPUT CONTROL CIRCUIT .............................................................. 243 13.1 Buzzer Output Control Circuit Functions .................................................................. 243 13.2 Buzzer Output Control Circuit Configuration ............................................................ 243 13.3 Buzzer Output Function Control Registers ............................................................... 244 ...
Page 20
CHAPTER 17 SERIAL INTERFACE CHANNEL 1 ....................................................................... 409 17.1 Serial Interface Channel 1 Functions ......................................................................... 409 17.2 Serial Interface Channel 1 Configuration ................................................................... 410 17.3 Serial Interface Channel 1 Control Registers ............................................................ 413 17.4 Serial Interface Channel 1 Operations ....................................................................... ...
Page 21
PROM Programming ...................................................................................................... 497 22.2.1 Operating modes ................................................................................................................ 497 22.2.2 PROM write procedure ....................................................................................................... 498 22.2.3 PROM read procedure ....................................................................................................... 500 22.3 Erasure Characteristics (for PD78P014DW, 78P014YDW) ..................................... 501 22.4 Opaque Film on Erasure Window (for PD78P014DW, 78P014YDW) .................... ...
Page 22
[MEMO] 22 ...
Page 23
Figure No. 3-1 Pin Input/Output Circuit List .............................................................................................................. 4-1 Pin Input/Output Circuit List .............................................................................................................. 5-1 Memory Map ( PD78011B, 78011BY) ............................................................................................. 5-2 Memory Map ( PD78012B, 78012BY) ............................................................................................. 5-3 Memory Map ( PD78013, 78013Y) .................................................................................................. 5-4 Memory Map ( PD78014, ...
Page 24
Figure No. 7-4 External Circuit of Main System Clock Oscillator .............................................................................. 160 7-5 External Circuit of Subsystem Clock Oscillator ................................................................................. 160 7-6 Examples of Resonator with Bad Connection ................................................................................... 161 7-7 Main System Clock Stop Function .................................................................................................... 165 7-8 System ...
Page 25
Figure No. 9-13 Square-Wave Output Operation Timings .......................................................................................... 219 9-14 8-Bit Timer Register Start Timings .................................................................................................... 220 9-15 External Event Counter Operation Timings ...................................................................................... 220 9-16 Timings after Compare Register Change during Timer Count Operation ......................................... 221 10-1 Watch Timer ...
Page 26
Figure No. 15-11 Example of Serial Bus Configuration with SBI .................................................................................. 284 15-12 SBI Transfer Timings ........................................................................................................................ 286 15-13 Bus Release Signal ........................................................................................................................... 287 15-14 Command Signal .............................................................................................................................. 287 15-15 Address ............................................................................................................................................. 288 15-16 Slave Selection with Address ............................................................................................................ 288 ...
Page 27
Figure No. 16-19 Data .................................................................................................................................................. 350 16-20 Acknowledge Signal .......................................................................................................................... 351 16-21 Busy Signal, Ready Signal ................................................................................................................ 352 16-22 RELT, CMDT, RELD and CMDD Operations (Master) ..................................................................... 357 16-23 RELD and CMDD Operations (Slave) ............................................................................................... 357 16-24 ACKT Operation ................................................................................................................................ ...
Page 28
Figure No. 17-10 Basic Transmit Mode Operation Timings .......................................................................................... 430 17-11 Basic Transmit Mode Flowchart ........................................................................................................ 431 17-12 Buffer RAM Operation in 6-Byte Transmission (in Basic Transmit Mode) ........................................ 432 17-13 Repeat Transmit Mode Operation Timings ....................................................................................... 434 17-14 Repeat ...
Page 29
Figure No. 20-1 Oscillation Stabilization Time Select Register Format ...................................................................... 484 20-2 HALT Mode Clear upon Interrupt Request Generation ..................................................................... 486 20-3 HALT Mode Clear upon RESET Input .............................................................................................. 487 20-4 STOP Mode Clear upon Interrupt Request Generation .................................................................... 489 ...
Page 30
[MEMO] 30 ...
Page 31
Table No. 1-1 Differences among PD78011B, 78012B, 78013, 78014 and PD78011B(A), 78012B(A), 78013(A), 78014(A) .......................................................................................................................... 1-2 Mask Options in Mask ROM Versions .............................................................................................. 2-1 Mask Options in Mask ROM Versions .............................................................................................. 3-1 Pin Input/Output Circuit Types .......................................................................................................... 4-1 Pin Input/Output ...
Page 32
Table No. 9-10 Square-Wave Output Ranges when 2-Channel 8-Bit Timer/Event Counters (TM1 and TM2) are Used as 16-Bit Tmer/Event Counter ........................................................................................... 219 10-1 Interval Timer Interval Time .............................................................................................................. 223 10-2 Watch Timer Configuration ............................................................................................................... 224 10-3 Interval Timer Interval Time ...
Page 33
Table No. 20-1 HALT Mode Operating Status ........................................................................................................... 485 20-2 Operation after HALT Mode Clear .................................................................................................... 487 20-3 STOP Mode Operating Status .......................................................................................................... 488 20-4 Operation after STOP Mode Clear .................................................................................................... 490 21-1 Hardware Status after Reset ............................................................................................................. 493 22-1 ...
Page 34
[MEMO] 34 ...
Page 35
CHAPTER 1 OUTLINE ( PD78014 Subseries) CHAPTER 1 OUTLINE ( PD78014 Subseries) 1.1 Features • On-chip large-capacity ROM and RAM Item Program Memory Part (ROM) Number PD78011B 8 Kbytes PD78012B 16 Kbytes PD78013 24 Kbytes PD78014 32 Kbytes Note 1 ...
Page 36
CHAPTER 1 OUTLINE ( PD78014 Subseries) 1.2 Application Fields For the PD78011B, 78012B, 78013, 78014, and 78P014 Telephone, VCR, audio system, camera, home electric appliances, etc. For the PD78011B(A), 78012B(A), 78013(A), and 78014(A) Automobile electronic equipment, gas detection breaker, safety ...
Page 37
CHAPTER 1 OUTLINE ( PD78014 Subseries) 1.4 Quality Grade Part Number PD78011BCW- 64-pin plastic shrink DIP (750 mils) PD78011BGC- -AB8 64-pin plastic QFP (14 PD78012BCW- 64-pin plastic shrink DIP (750 mils) PD78012BGC- -AB8 64-pin plastic QFP (14 PD78013CW- 64-pin plastic ...
Page 38
CHAPTER 1 OUTLINE ( PD78014 Subseries) 1.5 Pin Configurations (Top View) (1) Normal operating mode • 64-pin plastic shrink DIP (750 mils) PD78011BCW- , 78012BCW- PD78013CW- , 78014CW- PD78011BCW(A)- PD78013CW(A)- , 78014CW(A)- • 64-pin ceramic shrink DIP with window (750 ...
Page 39
CHAPTER 1 OUTLINE ( PD78014 Subseries) • 64-pin plastic QFP (14 PD78011BGC- -AB8, 78012BGC- PD78013GC- -AB8, 78014GC- PD78011BGC(A)- PD78013GC(A)- -AB8, 78014GC(A P30/TO0 1 P31/TO1 ...
Page 40
CHAPTER 1 OUTLINE ( PD78014 Subseries A15 : Address Bus AD0 to AD7 : Address/Data Bus ANI0 to ANI7 : Analog Input ASTB : Address Strobe AV : Analog Power Supply Analog Reference Voltage REF ...
Page 41
CHAPTER 1 OUTLINE ( PD78014 Subseries) (2) PROM programming mode • 64-pin plastic shrink DIP (750 mils) PD78P014CW • 64-pin ceramic shrink DIP with window (750 mils) PD78P014DW Cautions 1. (L) : Connect individually Connect ...
Page 42
CHAPTER 1 OUTLINE ( PD78014 Subseries) • 64-pin plastic QFP (14 PD78P014GC-AB8 ...
Page 43
CHAPTER 1 OUTLINE ( PD78014 Subseries) 1.6 78K/0 Series Expansion The following shows the 78K/0 Series products development. Subseries names are shown inside frames. Control PD78075B 100-pin PD78078 100-pin PD78070A 100-pin 100-pin PD780058 80-pin PD78058F 80-pin PD78054 80-pin PD780034 64-pin ...
Page 44
CHAPTER 1 OUTLINE ( PD78014 Subseries) The following table shows the differences among subseries functions. Function ROM Part Number Capacity 8-bit 16-bit Watch WDT Control PD78075B 32K to 40K 4ch PD78078 48K to 60K PD78070A — PD780058 24K to 60K ...
Page 45
CHAPTER 1 OUTLINE ( PD78014 Subseries) 1.7 Block Diagram TO0/P30 16-bit TIMER/ EVENT COUNTER TI0/INTP0/P00 TO1/P31 8-bit TIMER/ EVENT COUNTER 1 TI1/P33 TO2/P32 8-bit TIMER/ EVENT COUNTER 2 TI2/P34 WATCHDOG TIMER WATCH TIMER SI0/SB0/P25 SERIAL SO0/SB1/P26 INTERFACE 0 SCK0/P27 SI1/P20 ...
Page 46
CHAPTER 1 OUTLINE ( PD78014 Subseries) 1.8 Outline of Function Part Number Item Internal ROM memory High-speed RAM Buffer RAM Memory space General registers Minimum When main system instruction clock selected execution When subsystem time clock selected Instruction set I/O ...
Page 47
CHAPTER 1 OUTLINE ( PD78014 Subseries) Part Number Item Timer output Clock output Buzzer output Vectored Maskable interrupt Non-maskable sources Software Test input Power supply voltage Operating ambient temperature Package 1.9 Differences among PD78011B, 78012B, 78013, 78014 and PD78011B(A), 78012B(A), ...
Page 48
CHAPTER 1 OUTLINE ( PD78014 Subseries) 1.10 Mask Options The mask ROM versions ( PD78011B, PD78012B, PD78013, PD78014) have the mask options. By specifying the mask options when ordering, the pull-up resistors and pull-down resistors listed in Table 1-2 can ...
Page 49
CHAPTER 2 OUTLINE ( PD78014Y Subseries) CHAPTER 2 OUTLINE ( PD78014Y Subseries) 2.1 Features • On-chip large-capacity ROM and RAM Item Program Memory Part (ROM) Number PD78011BY 8 Kbytes PD78012BY 16 Kbytes PD78013Y 24 Kbytes PD78014Y 32 Kbytes Note 1 ...
Page 50
CHAPTER 2 OUTLINE ( PD78014Y Subseries) 2.2 Application Fields Telephone, VCR, audio system, camera, home electric appliances, etc. 2.3 Ordering Information Part Number PD78011BYCW- PD78011BYGC- -AB8 PD78012BCW- PD78012BYGC- -AB8 PD78013YCW- PD78013YGC- -AB8 PD78014YCW- PD78014YGC- -AB8 PD78P014YCW PD78P014YDW PD78P014YGC-AB8 Remark is ...
Page 51
CHAPTER 2 OUTLINE ( PD78014Y Subseries) 2.5 Pin Configurations (Top View) (1) Normal operating mode • 64-pin plastic shrink DIP (750 mils) PD78011BYCW- , 78012BYCW- PD78013YCW- , 78014YCW- • 64-pin ceramic shrink DIP with window (750 mils) PD78P014YDW P22/SCK1 P24/BUSY ...
Page 52
CHAPTER 2 OUTLINE ( PD78014Y Subseries) • 64-pin plastic QFP (14 14 mm) PD78011BYGC- -AB8, 78012BYGC- PD78013YGC- -AB8, 78014YGC P30/TO0 1 P31/TO1 2 P32/TO2 ...
Page 53
CHAPTER 2 OUTLINE ( PD78014Y Subseries A15 : Address Bus AD0 to AD7 : Address/Data Bus ANI0 to ANI7 : Analog Input ASTB : Address Strobe AV : Analog Power Supply Analog Reference Voltage REF ...
Page 54
CHAPTER 2 OUTLINE ( PD78014Y Subseries) (2) PROM programming mode • 64-pin plastic shrink DIP (750 mils) PD78P014YCW • 64-pin ceramic shrink DIP with window (750 mils) PD78P014YDW Cautions 1. (L) : Connect individually Connect ...
Page 55
CHAPTER 2 OUTLINE ( PD78014Y Subseries) • 64-pin plastic QFP (14 14 mm) PD78P014YGC-AB8 ...
Page 56
CHAPTER 2 OUTLINE ( PD78014Y Subseries) 2.6 78K/0 Series Expansion The following shows the 78K/0 Series products development. Subseries names are shown inside frames. Control PD78075B 100-pin PD78078 100-pin PD78070A 100-pin 100-pin PD780058 80-pin PD78058F 80-pin PD78054 80-pin PD780034 64-pin ...
Page 57
CHAPTER 2 OUTLINE ( PD78014Y Subseries) The following table shows the differences among Y subseries functions. Function ROM Part number Capacity Control PD78075BY 32K to 40K PD78078Y 48K to 60K PD78070AY — PD780018AY 48K to 60K PD780058Y 24K to 60K ...
Page 58
CHAPTER 2 OUTLINE ( PD78014Y Subseries) 2.7 Block Diagram TO0/P30 16-bit TIMER/ EVENT COUNTER TI0/INTP0/P00 TO1/P31 8-bit TIMER/ EVENT COUNTER 1 TI1/P33 TO2/P32 8-bit TIMER/ EVENT COUNTER 2 TI2/P34 WATCHDOG TIMER WATCH TIMER SI0/SB0/SDA0/P25 SERIAL SO0/SB1/SDA1/P26 INTERFACE 0 SCK0/SCL/P27 SI1/P20 ...
Page 59
CHAPTER 2 OUTLINE ( PD78014Y Subseries) 2.8 Outline of Function Part Number Item Internal ROM memory High-speed RAM Buffer RAM Memory space General registers Minimum When main system instruction clock selected execution When subsystem time clock selected Instruction set I/O ...
Page 60
CHAPTER 2 OUTLINE ( PD78014Y Subseries) Part Number Item Timer output Clock output Buzzer output Vectored Maskable interrupt Non-maskable sources Software Test input Power supply voltage Operating ambient temperature Package 60 PD78011BY PD78012BY PD78013Y 3 outputs: (14-bit PWM generation possible ...
Page 61
CHAPTER 2 OUTLINE ( PD78014Y Subseries) 2.9 Mask Options The mask ROM versions ( PD78011BY, specifying the mask options when ordering, the pull-up resistors and pull-down resistors listed in Table 2-1 can be incorporated. When these resistors are necessary, the ...
Page 62
CHAPTER 2 OUTLINE ( PD78014Y Subseries) [MEMO] 62 ...
Page 63
CHAPTER 3 PIN FUNCTION ( PD78014 Subseries) CHAPTER 3 PIN FUNCTION ( PD78014 Subseries) 3.1 Pin Function List 3.1.1 Normal operating mode pins (1) Port pins (1/2) Pin Name Input/ Output P00 Input Port 0 P01 Input/ 5-bit input/output port ...
Page 64
CHAPTER 3 PIN FUNCTION ( PD78014 Subseries) (1) Port pins (2/2) Pin Name Input/ Output P40 to P47 Input/ Port 4 Output 8-bit input/output port. Input/output specifiable in 8-bit wise. When used as an input port, an on-chip pull-up resistor ...
Page 65
CHAPTER 3 PIN FUNCTION ( PD78014 Subseries) (2) Non-Port Pins (1/2) Pin Name Input/ Output INTP0 Input External interrupt request inputs with specifiable valid edges (rising INTP1 edge, falling edge, both rising and falling edges). INTP2 INTP3 External interrupt request ...
Page 66
CHAPTER 3 PIN FUNCTION ( PD78014 Subseries) (2) Non-Port Pins (2/2) Pin Name Input/ Output ANI0 to ANI7 Input A/D converter analog input. AV Input A/D converter reference voltage input. REF AV — A/D converter analog power supply. Connect to ...
Page 67
CHAPTER 3 PIN FUNCTION ( PD78014 Subseries) 3.2 Description of Pin Functions 3.2.1 P00 to P04 (Port 0) These are 5-bit input/output ports. Besides serving as input/output ports, they function as an external interrupt request input, an external count clock ...
Page 68
CHAPTER 3 PIN FUNCTION ( PD78014 Subseries) 3.2.2 P10 to P17 (Port 1) These are 8-bit input/output ports. Besides serving as input/output ports, they function as an A/D converter analog input. The following operating modes can be specified bit-wise. (1) ...
Page 69
CHAPTER 3 PIN FUNCTION ( PD78014 Subseries) 3.2.3 P20 to P27 (Port 2) These are 8-bit input/output ports. Besides serving as input/output ports, they function as data input/output to/ from the serial interface, clock input/output, automatic transmit/receive busy input, and ...
Page 70
CHAPTER 3 PIN FUNCTION ( PD78014 Subseries) 3.2.4 P30 to P37 (Port 3) These are 8-bit input/output ports. Beside serving as input/output ports, they function as timer input/output, clock output and buzzer output. The following operating modes can be specified ...
Page 71
CHAPTER 3 PIN FUNCTION ( PD78014 Subseries) 3.2.5 P40 to P47 (Port 4) These are 8-bit input/output ports. Besides serving as input/output ports, they function as address/data bus. Test input flag (KRIF) is set falling edge detection. ...
Page 72
CHAPTER 3 PIN FUNCTION ( PD78014 Subseries) 3.2.7 P60 to P67 (Port 6) These are 8-bit output dedicated ports. Besides serving as input/output port, they have control functions in external memory expansion mode. P60 to P63 can drive LEDs directly. ...
Page 73
CHAPTER 3 PIN FUNCTION ( PD78014 Subseries) 3.2.13 XT1 and XT2 Crystal resonator connection pins for subsystem clock oscillation. For external clock supply, input it to XT1 and its inverted signal to XT2. 3.2. Positive power supply pin ...
Page 74
CHAPTER 3 PIN FUNCTION ( PD78014 Subseries) 3.3 Input/Output Circuit and Recommended Connection of Unused Pins Table 3-1 shows the input/output circuit types of pins and the recommended conditions for unused pins. Refer to Figure 3-1 for the configuration of ...
Page 75
CHAPTER 3 PIN FUNCTION ( PD78014 Subseries) Table 3-1. Pin Input/Output Circuit Types (2/2) Pin Name Input/Output Circuit Type RESET 2 XT2 16 AV — REF (Mask ROM Version) V (PROM Version) PP Input/Output Recommended ...
Page 76
CHAPTER 3 PIN FUNCTION ( PD78014 Subseries) Figure 3-1. Pin Input/Output Circuit List (1/2) Type 2 IN Schmitt-triggered input with hysteresis characteristics Type 5-A pull-up enable V DD data output N-ch disable input enable Type 5-E pull-up enable V DD ...
Page 77
CHAPTER 3 PIN FUNCTION ( PD78014 Subseries) Figure 3-1. Pin Input/Output Circuit List (2/2) Type 13 data output disable Middle-High Voltage Input Buffer Type 13-B data N-ch output disable V P-ch RD Middle-High Voltage Input Buffer Type ...
Page 78
CHAPTER 3 PIN FUNCTION ( PD78014 Subseries) [MEMO] 78 ...
Page 79
CHAPTER 4 PIN FUNCTION ( PD78014Y Subseries) CHAPTER 4 PIN FUNCTION ( PD78014Y Subseries) 4.1 Pin Function List 4.1.1 Normal operating mode pins (1) Port pins (1/2) Pin Name Input/ Output P00 Input Port 0 P01 Input/ 5-bit input/output port ...
Page 80
CHAPTER 4 PIN FUNCTION ( PD78014Y Subseries) (1) Port pins (2/2) Pin Name Input/ Output P40 to P47 Input/ Port 4 Output 8-bit input/output port. Input/output specifiable in 8-bit units. When used as an input port, an on-chip pull-up resistor ...
Page 81
CHAPTER 4 PIN FUNCTION ( PD78014Y Subseries) (2) Non-Port Pins (1/2) Pin Name Input/ Output INTP0 Input External interrupt request inputs with specifiable valid edges (rising INTP1 edge, falling edge, both rising and falling edges). INTP2 INTP3 External interrupt request ...
Page 82
CHAPTER 4 PIN FUNCTION ( PD78014Y Subseries) (2) Non-Port Pins (2/2) Pin Name Input/ Output ANI0 to ANI7 Input A/D converter analog input. AV Input A/D converter reference voltage input. REF AV — A/D converter analog power supply. Connect to ...
Page 83
CHAPTER 4 PIN FUNCTION ( PD78014Y Subseries) 4.2 Description of Pin Functions 4.2.1 P00 to P04 (Port 0) These are 5-bit input/output ports. Besides serving as input/output ports, they function as an external interrupt request input, an external count clock ...
Page 84
CHAPTER 4 PIN FUNCTION ( PD78014Y Subseries) 4.2.2 P10 to P17 (Port 1) These are 8-bit input/output ports. Besides serving as input/output ports, they function as an A/D converter analog input. The following operating modes can be specified bit-wise. (1) ...
Page 85
CHAPTER 4 PIN FUNCTION ( PD78014Y Subseries) 4.2.3 P20 to P27 (Port 2) These are 8-bit input/output ports. Besides serving as input/output ports, they function as data input/output to/ from the serial interface, clock input/output, automatic transmit/receive busy input, and ...
Page 86
CHAPTER 4 PIN FUNCTION ( PD78014Y Subseries) 4.2.4 P30 to P37 (Port 3) These are 8-bit input/output ports. Beside serving as input/output ports, they function as timer input/output, clock output and buzzer output. The following operating modes can be specified ...
Page 87
CHAPTER 4 PIN FUNCTION ( PD78014Y Subseries) 4.2.5 P40 to P47 (Port 4) These are 8-bit input/output ports. Besides serving as input/output ports, they function as address/data bus. The test input flag (KRIF) is set falling edge ...
Page 88
CHAPTER 4 PIN FUNCTION ( PD78014Y Subseries) 4.2.7 P60 to P67 (Port 6) These are 8-bit input/output ports. Besides serving as an input/output port, they have control functions in external memory expansion mode. P60 to P63 can drive LEDs directly. ...
Page 89
CHAPTER 4 PIN FUNCTION ( PD78014Y Subseries) 4.2.13 XT1 and XT2 Crystal resonator connection pins for subsystem clock oscillation. For external clock supply, input it to XT1 and its inverted signal to XT2. 4.2. Positive power supply pin ...
Page 90
CHAPTER 4 PIN FUNCTION ( PD78014Y Subseries) 4.3 Input/Output Circuit and Recommended Connection of Unused Pins Table 4-1 shows the input/output circuit types of pins and the recommended conditions for unused pins. Refer to Figure 4-1 for the configuration of ...
Page 91
CHAPTER 4 PIN FUNCTION ( PD78014Y Subseries) Table 4-1. Pin Input/Output Circuit Types (2/2) Pin Name Input/Output RESET 2 XT2 16 AV — REF (Mask ROM Version) V (PROM Version) PP Input/Output Recommended Connection for ...
Page 92
CHAPTER 4 PIN FUNCTION ( PD78014Y Subseries) Figure 4-1. Pin Input/Output Circuit List (1/2) Type 2 IN Schmitt-triggered input with hysteresis characteristics Type 5-A pull-up enable V DD data output N-ch disable input enable Type 5-E pull-up enable V DD ...
Page 93
CHAPTER 4 PIN FUNCTION ( PD78014Y Subseries) Figure 4-1. Pin Input/Output Circuit List (2/2) Type 13 data output disable Middle-High Voltage Input Buffer Type 13-B data N-ch output disable V P-ch RD Middle-High Voltage Input Buffer Type ...
Page 94
CHAPTER 4 PIN FUNCTION ( PD78014Y Subseries) [MEMO] 94 ...
Page 95
Memory Spaces The PD78014 and 78014Y Subseries can each access a memory space of 64 Kbytes. Figures 5-1 to 5-5 show memory maps. Figure 5-1. Memory Map ( PD78011B, 78011BY) FFFFH General Registers FEFFH ...
Page 96
Figure 5-2. Memory Map ( PD78012B, 78012BY) FFFFH General Registers FEFFH FEE0H FEDFH Internal High-Speed RAM FD00H FCFFH FAE0H FADFH Data Memory Space FAC0H FABFH FA80H FA7FH Program Memory 3FFFH ...
Page 97
CHAPTER 5 CPU ARCHITECTURE Figure 5-3. Memory Map ( PD78013, 78013Y) FFFFH Special Function Registers (SFR General Registers FEFFH 32 FEE0H FEDFH Internal High-Speed RAM FB00H FAFFH FAE0H FADFH Data Memory Space FAC0H FABFH FA80H ...
Page 98
Figure 5-4. Memory Map ( PD78014, 78014Y) FFFFH General Registers FEFFH FEE0H FEDFH Internal High-Speed RAM FB00H FAFFH FAE0H FADFH Data Memory Space FAC0H FABFH FA80H FA7FH Program Memory 7FFFH ...
Page 99
Figure 5-5. Memory Map ( PD78P014, 78P014Y) FFFFH Special Function Registers (SFR General Registers FEFFH 32 FEE0H FEDFH Internal High-Speed RAM FB00H FAFFH FAE0H FADFH Data Memory Space FAC0H FABFH FA80H FA7FH External Memory Program ...
Page 100
Internal program memory space Internal program memory store programs and table data. Normally, they are addressed with a program counter (PC). The PD78014 and 78014Y Subseries contain internal ROM (or PROM) in each product having the capacities shown below. ...
Page 101
Internal data memory space The PD78014 and 78014Y Subseries incorporate the following RAMs. (1) Internal high-speed RAM The PD78014 and 78014Y Subseries incorporate the following capacity of internal high-speed RAM in each product. Table 5-3. Internal High-Speed RAM Capacities ...
Page 102
Processor Registers The PD78014 and 78014Y Subseries incorporate the following processor registers. 5.2.1 Control registers The control registers control the program sequence, statuses and stack memory. A program counter (PC), a program status word (PSW) and a stack pointer ...
Page 103
CHAPTER 5 CPU ARCHITECTURE (a) Interrupt enable flag (IE) This flag controls interrupt request acknowledge operations of CPU. When the IE is set to interrupt disabled (DI) status. All interrupt requests except non-maskable interrupt are disabled. When ...
Page 104
Stack pointer (SP) This is a 16-bit register to hold the start address of the memory stack area. Only the internal high-speed RAM area can be set as the stack area. Internal high-speed RAM of each product is as ...
Page 105
CHAPTER 5 CPU ARCHITECTURE Figure 5-9. Data to be Saved to Stack Memory PUSH rp Instruction SP SP–2 Register Pair Lower SP–2 SP–1 Register Pair Upper SP Figure 5-10. Data to be Reset from Stack Memory POP rp Instruction SP ...
Page 106
General registers A general register is mapped at particular addresses (FEE0H to FEFFH) of the data memory. It consists of 4 banks, each bank consisting of eight 8-bit registers ( and H). Each ...
Page 107
Figure 5-11. General Register Configuration BANK0 BANK1 BANK2 ...
Page 108
Special function register (SFR) Unlike a general register, each special function register has special functions allocated in the FF00H to FFFFH area. The special function register can be manipulated, like the general register, with the operation, transfer ...
Page 109
Table 5-5. Special Function Register List (1/2) Address Special Function Register (SFR) Name FF00H Port 0 FF01H Port 1 FF02H Port 2 FF03H Port 3 FF04H Port 4 FF05H Port 5 FF06H Port 6 FF10H 16-bit compare register FF11H FF12H ...
Page 110
Table 5-5. Special Function Register List (2/2) Address Special Function Register (SFR) Name FF60H Serial operating mode register 0 FF61H Serial bus interface control register FF62H Slave address register FF63H Interrupt timing specify register FF68H Serial operating mode register 1 ...
Page 111
Instruction Address Addressing An instruction address is determined by program counter (PC) contents. The PC contents are normally incremented (+1 for each byte) automatically according to the number of bytes of an instruction to be fetched each time another ...
Page 112
Immediate addressing [Function] Immediate data in the instruction word is transferred to the program counter (PC) and branched. This function is carried out when the CALL ! addr16 addr16, or CALLF ! addr11 instruction is executed. CALL ...
Page 113
Table indirect addressing [Function] Table contents (branch destination address) of the particular location to be addressed by bits the immediate data of an operation code are transferred to the program counter (PC) and branched. Table ...
Page 114
Register addressing [Function] Register pair (AX) contents to be specified with an instruction word are transferred to the program counter (PC) and branched. This function is carried out when the BR AX instruction is executed. [Illustration ...
Page 115
Operand Address Addressing 5.4.1 Data memory addressing Addressing is a method to specify the instruction address to be executed next and the register and memory address to be manipulated when instructions are executed. The instruction address to be executed ...
Page 116
Figure 5-13. Data Memory Addressing ( PD78012B, 78012BY Special Function Registers (SFR) 256 8 bits ...
Page 117
CHAPTER 5 CPU ARCHITECTURE Figure 5-14. Data Memory Addressing ( PD78013, 78013Y Special Function Registers (SFR) 256 8 bits ...
Page 118
Figure 5-15. Data Memory Addressing ( PD78014, 78014Y Special Function Registers (SFR) 256 8 bits ...
Page 119
Figure 5-16. Data Memory Addressing ( PD78P014, 78P014Y Special Function Registers (SFR) 256 8 bits ...
Page 120
Implied addressing [Function] The register which functions as an accumulator (A and AX) in the general register is automatically (implicitly) addressed. Of the PD78014 and 78014Y Subseries instruction words, the following instructions employ implied addressing. Instruction MULU A register ...
Page 121
Register addressing [Function] The general register is accessed as an operand. The general register to be accessed is specified with register bank select flags (RBS0 and RBS1) and register specify code (Rn and RPn) in the instruction code. Register ...
Page 122
Direct addressing [Function] The memory indicated by immediate data in an instruction word is directly addressed. [Operand format] I dentifier addr16 [Description example] MOV A, ! 0FE00H; when setting ! addr16 to FE00H Instruction code 1 [Illustration] 7 122 ...
Page 123
Short direct addressing [Function] The memory to be manipulated in the fixed space is directly addressed with 8-bit data in an instruction word. The fixed space where this addressing is applied to is the 256-byte space FE20H to FF1FH. ...
Page 124
MOV 0FE30H, #50H; when setting saddr to FE30H and immediate data to 50H Instruction code 0 [Illustration code saddr-offset 15 Effective address When 8-bit immediate data is 20H to FFH, When ...
Page 125
Special function register (SFR) addressing [Function] The memory-mapped special function register (SFR) is addressed with 8-bit immediate data in an instruction word. This addressing is applied to the 240-byte spaces FF00H to FFCFH and FFE0H to FFFFH. However, the ...
Page 126
Register indirect addressing [Function] The memory is addressed with the contents of the register pair specified as an operand. The register pair to be accessed is specified with the register bank select flag (RBS0 and RBS1) and the register ...
Page 127
Based addressing [Function] 8-bit immediate data is added to the contents of the base register, that is, the HL register pair, and the sum is used to address the memory. The HL register pair to be accessed is in ...
Page 128
Based indexed addressing [Function] The register contents specified in an instruction are added to the contents of the base register, that is, the HL register pair, and the sum is used to address the memory. The ...
Page 129
Port Functions The PD78014 and 78014Y Subseries each incorporate two input ports and fifty-one input/output ports. Figure 6-1 shows the port types. Every port is capable of 1-bit and 8-bit manipulations and can carry out considerably varied control operations. ...
Page 130
Table 6-1. Port Functions ( PD78014 Subseries) (1/2) Pin Name P00 Port 0. P01 5-bit input/output port. P02 P03 P04 P10 to P17 Port 1. 8-bit input/output port. Input/output specifiable bit-wise. If used as an input port, on-chip pull-up resistor ...
Page 131
Table 6-1. Port Functions ( PD78014 Subseries) (2/2) Pin Name P60 Port 6. P61 8-bit input/output port. P62 Input/output specifiable bit-wise. P63 P64 P65 P66 P67 CHAPTER 6 PORT FUNCTIONS Function N-ch open-drain input/output port. On-chip pull-up resistor can be ...
Page 132
Table 6-2. Port Functions ( PD78014Y Subseries) (1/2) Pin Name P00 Port 0. P01 5-bit input/output port. P02 P03 P04 P10 to P17 Port 1. 8-bit input/output port. Input/output specifiable bit-wise. If used as an input port, on-chip pull-up resistor ...
Page 133
Table 6-2. Port Functions ( PD78014Y Subseries) (2/2) Pin Name P60 Port 6. P61 8-bit input/output port. P62 Input/output specifiable bit-wise. P63 P64 P65 P66 P67 CHAPTER 6 PORT FUNCTIONS Function N-ch open-drain input/output port. On-chip pull-up resistor can be ...
Page 134
Port Block Diagram A port consists of the following hardware. Item Control register Port mode register Pull-up resistor option register Memory expansion mode register Key return mode register Port Total: 53 ports (2 inputs, 51 inputs/outputs) Pull-up resistor • ...
Page 135
CHAPTER 6 PORT FUNCTIONS Figure 6-3. P01 to P03 Block Diagrams WR PUO PUO0 RD WR PORT Output Latch (P01 to P03 PM01 to PM03 PUO : Pull-up resistor option register PM : Port mode register RD : ...
Page 136
Port 1 Port 8-bit input/output port with output latch. P10 to P17 pins can be set to the input mode/output mode bit-wise with a port mode register 1 (PM1). When P10 to P17 pins are used ...
Page 137
Port 2 ( PD78014 Subseries) Port 8-bit input/output port with output latch. P20 to P27 pins can be set to the input mode/output mode bit-wise with the port mode register 2 (PM2). When P20 to P27 ...
Page 138
Figure 6-7. P22 and P27 Block Diagrams ( PD78014 Subseries) WR PUO PUO2 RD WR PORT Output Latch (P22, P27 PM22, PM27 Alternate Function PUO : Pull-up resistor option register PM : Port mode register RD : Port ...
Page 139
Port 2 ( PD78014Y Subseries) Port 8-bit input/output port with output latch. P20 to P27 pins can be set to the input mode/output mode bit-wise with the port mode register 2 (PM2). When P20 to P27 ...
Page 140
Figure 6-9. P22 and P27 Block Diagrams ( PD78014Y Subseries) WR PUO PUO2 RD WR PORT Output Latch (P22, P27 PM22, PM27 Alternate Function PUO : Pull-up resistor option register PM : Port mode register RD : Port ...
Page 141
Port 3 Port 8-bit input/output port with output latch. P30 to P37 pins can be set to the input mode/output mode bit-wise with the port mode register (PM3). When P30 to P37 pins are used as ...
Page 142
Port 4 Port 8-bit input/output port with output latch. P40 to P47 pins can be set to the input mode/output mode in 8-bit units with the memory expansion mode register (MM). When P40 to P47 pins ...
Page 143
Port 5 Port 8-bit input/output port with output latch. P50 to P57 pins can be set to the input mode/output mode bit-wise with the port mode register 5 (PM5). When P50 to P57 pins are used ...
Page 144
Port 6 Port 8-bit input/output port with output latches. P60 to P67 pins can be set to either input mode or output mode in 1-bit units with port mode register 6 (PM6). This port has the ...
Page 145
CHAPTER 6 PORT FUNCTIONS Figure 6-14. P60 to P63 Block Diagrams RD WR PORT Output Latch (P60 to P63 PM60 to PM63 PM : Port mode register RD : Port 6 read signal WR : Port 6 write ...
Page 146
Port Function Control Registers The following four types of registers control the ports. • Port mode registers (PM0, PM1, PM2, PM3, PM5, PM6) • Pull-up resistor option register (PUO) • Memory expansion mode register (MM) • Key return mode ...
Page 147
Table 6-5. Port Mode Register and Output Latch Setting when Alternate Function is Used Pin Name Alternate Function Function Input/ Name Output P00 INTP0 Input TI0 Input P01 to P03 INTP1 to INTP3 Input P04 Note 1 XT1 Input P10 ...
Page 148
Figure 6-16. Port Mode Register Format Symbol PM0 PM1 PM17 PM16 PM15 PM14 PM2 PM27 PM26 PM25 PM24 PM3 PM37 PM36 PM35 PM34 PM5 PM57 PM56 PM55 PM54 PM6 PM67 PM66 PM65 ...
Page 149
Pull-up resistor option register (PUO) This register is used to set whether to use an on-chip pull-up resistor at each port or not. An on-chip pull-up resistor is internally used only for the bits that are set to the ...
Page 150
Memory expansion mode register (MM) The registers are used to set port 4 input/output set with a 1-bit or 8-bit memory manipulation instruction. RESET input sets MM to 10H. Figure 6-18. Memory Expansion Mode Register Format Symbol ...
Page 151
Key return mode register (KRM) The registers are used to set standby mode release enable/disable with the key return signal (falling edge detection of port 4). KRM is set with a 1-bit or 8-bit memory manipulation instruction. RESET input ...
Page 152
Port Function Operations Port operations differ depending on whether the input or output mode is set, as shown below. 6.4.1 Writing to input/output port (1) Output mode A value is written to the output latch by a transfer instruction, ...
Page 153
Operations on input/output port (1) Output mode An operation is performed on the output latch contents, and the result is written to the output latch. The output latch contents are output from the pins. Once data is written to ...
Page 154
Mask Options Mask ROM versions can contain a pull-up resistor in P60 to P63 pins bit-wise with the mask option. The PD78P014 and 78P014Y have no mask option and do not contain a pull-up resistor for P60 to P63 ...
Page 155
Clock Generator Functions The clock generator generates the clock to be supplied to the CPU and peripheral hardware. The following two types of system clock oscillators are available. (1) Main system clock oscillator Oscillates at frequencies of 1.0 to ...
Page 156
FRC XT1/P04 Subsystem f XT clock oscillator circuit XT2 X1 Main system f X Prescaler clock oscil- lator circuit STOP Processor clock control register Figure 7-1. Clock Generator Block Diagram Watch timer, ...
Page 157
Clock Generator Control Register The clock generator is controlled by the processor clock control register (PCC). The PCC sets CPU clock selection, the ratio of division, main system clock oscillator operation/stop and subsystem clock oscillator on-chip feedback resistor enable/disable. ...
Page 158
Figure 7-3. Processor Clock Control Register Format Symbol <7> <6> <5> <4> PCC MCC FRC CLS CSS Notes 1. Bit 5 is Read Only. 2. When the CPU is operating on the subsystem clock, MCC should be used to stop ...
Page 159
The fastest instruction of the PD78014, 78014Y Subseries is executed by the CPU clock 4 clock. The relationship between the CPU clock (f ) and minimum instruction execution time is as shown in Table 7-2. CPU Table 7-2. Relationship between ...
Page 160
System Clock Oscillator 7.4.1 Main system clock oscillator The main system clock oscillator oscillates with a crystal resonator or a ceramic resonator (standard: 10.0 MHz) connected to the X1 and X2 pins. External clocks can be input to the ...
Page 161
Cautions 1. When using a main system clock oscillator and a subsystem clock oscillator, wire the portion enclosed in the dotted line areas in Figures 7-4 and 7-5 as follows to avoid adverse influence on the wiring capacitance. • Keep ...
Page 162
Figure 7-6. Examples of Resonator with Bad Connection (2/2) (c) High fluctuating current close to signal lines X2 X1 High current (e) Signal extracted X2 X1 Remark When using a subsystem clock, replace X1 and X2 with XT1 and XT2, ...
Page 163
Divider The divider divides the main system clock oscillator output (f 7.4.4 When no subsystem clocks are used not necessary to use subsystem clocks for low power consumption operations and watch operations, connect the XT1 and ...
Page 164
Clock Generator Operations The clock generator generates the following types of clocks and controls the CPU operating mode including the standby mode. • Main system clock f X • Subsystem clock f XT • CPU clock f CPU • ...
Page 165
Main system clock operations When operated with the main system clock (with bit 5 (CLS) of the processor clock control register (PCC) set to 0), the following operations are carried out by PCC setting. (a) Because the operation guarantee ...
Page 166
Figure 7-7. Main System Clock Stop Function (2/2) (b) Operation when MCC is set with main system clock operation MCC CSS “L” “L” CLS Main System Clock Oscillation Subsystem Clock Oscillation CPU Clock (c) Operation when CSS is set after ...
Page 167
Subsystem clock operations When operated with the subsystem clock (with bit 5 (CLS) of the processor clock control register (PCC) set to 1), the following operations are carried out. (a) The minimum instruction execution time remains constant (122 s ...
Page 168
Changing System Clock and CPU Clock Settings 7.6.1 Time required for switchover between system clock and CPU clock The system clock and CPU clock can be switched over by means of bits (PCC0 to PCC2) and ...
Page 169
System clock and CPU clock switching procedure This section describes switching procedure between system clock and CPU clock. Figure 7-8. System Clock and CPU Clock Switching V DD RESET Interrupt Request Signal System Clock CPU Clock (1)The CPU is ...
Page 170
CHAPTER 7 CLOCK GENERATOR ...
Page 171
CHAPTER 8 16-BIT TIMER/EVENT COUNTER CHAPTER 8 16-BIT TIMER/EVENT COUNTER 8.1 Outline of On-chip Timer in PD78014, 78014Y Subseries This section describes the 16-bit timer/event counter. First an outline of the built-in timer in the PD78014 and 78014Y Subseries and ...
Page 172
CHAPTER 8 16-BIT TIMER/EVENT COUNTER Table 8-1. Timer/Event Counter Operation Operation Interval timer mode External event counter Function Timer output PWM output Pulse width measurement Square-wave output Interrupt request Test input Notes 1. Watch timer can perform both watch timer ...
Page 173
CHAPTER 8 16-BIT TIMER/EVENT COUNTER (2) PWM output TM0 can generate 14-bit resolution PWM output. (3) Pulse width measurement TM0 can measure the pulse width of an externally input signal. (4) External event counter TM0 can measure the number of ...
Page 174
Figure 8-1. 16-Bit Timer/Event Counter (Timer Mode) Block Diagram 0 16-bit compare register (CR00) Match 16-bit timer register lower 8 bits (TM0L) TI0/P00/ Note 1 Clear INTP0 3 ...
Page 175
Figure 8-2. 16-Bit Timer/Event Counter (PWM Mode) Block Diagram 16-bit compare register (CR00 PWM pulse generator 16-bit timer register (TM0) 3 16-bit capture register (CR01) TCL06 TCL05 TCL04 Timer ...
Page 176
Figure 8-3. 16-Bit Timer/Event Counter Output Control Circuit Block Diagram LVR0 LVS0 TOC01 INTTM0 Edge TI0/P00/ detector INTP0 circuit 2 ES10, ES11 PWM pulse generator TMC01 to TMC03 Remark The circuitry enclosed by the dotted line is the output control ...
Page 177
CHAPTER 8 16-BIT TIMER/EVENT COUNTER (1) 16-bit compare register (CR00) CR00 is a 16-bit register for which the value set in the CR00 is constantly compared with the 16-bit timer register (TM0) count value, and an interrupt request (INTTM0) is ...
Page 178
CHAPTER 8 16-BIT TIMER/EVENT COUNTER 8.4 16-Bit Timer/Event Counter Control Registers The following six types of registers are used to control the 16-bit timer/event counter. • Timer clock select register 0 (TCL0) • 16-bit timer mode control register (TMC0) • ...
Page 179
CHAPTER 8 16-BIT TIMER/EVENT COUNTER Figure 8-4. Timer Clock Select Register 0 Format Symbol <7> TCL0 CLOE TCL06 TCL05 TCL04 TCL03 TCL02 TCL01 TCL00 Cautions 1. Setting of the INTP0/P00/TI0 pin valid edge is performed by external ...
Page 180
CHAPTER 8 16-BIT TIMER/EVENT COUNTER (2) 16-bit timer mode control register (TMC0) This register sets the 16-bit timer operating mode, the 16-bit timer register clear mode and output timing, and detects an overflow. TMC0 is set with a 1-bit or ...
Page 181
CHAPTER 8 16-BIT TIMER/EVENT COUNTER Figure 8-5. 16-Bit Timer Mode Control Register Format Symbol TMC0 OVF0 16-Bit Timer Register Overflow Detection 0 Overflow not detected 1 Overflow detected TMC03 TMC02 TMC01 Operating ...
Page 182
CHAPTER 8 16-BIT TIMER/EVENT COUNTER (3) 16-bit timer output control register (TOC0) This register controls the operation of the 16-bit timer/event counter output control circuit. It sets R-S type flip- flop (LV0) setting/resetting, the active level in PWM mode, output ...
Page 183
CHAPTER 8 16-BIT TIMER/EVENT COUNTER (4) Port mode register 3 (PM3) This register sets port 3 input/output bit-wise. When using the P30/TO0 pin for timer output, set PM30 and output latch of P30 to 0. PM3 is set with a ...
Page 184
CHAPTER 8 16-BIT TIMER/EVENT COUNTER (5) External interrupt mode register (INTM0) This register is used to set INTP0 to INTP2 valid edges. INTM0 is set with an 8-bit memory manipulation instruction. RESET input sets INTM0 value to 00H. Remarks 1. ...
Page 185
CHAPTER 8 16-BIT TIMER/EVENT COUNTER (6) Sampling clock select register (SCS) This register sets clocks which undergo clock sampling of valid edges to be input to INTP0. When remote controlled reception is carried out using INTP0, digital noise is removed ...
Page 186
CHAPTER 8 16-BIT TIMER/EVENT COUNTER 8.5 16-Bit Timer/Event Counter Operations 8.5.1 Interval timer operations By setting bits 2 and 3 (TMC02 and TMC03) of the 16-bit timer mode control register (TMC0 and 1, they are operated as an ...
Page 187
CHAPTER 8 16-BIT TIMER/EVENT COUNTER Figure 8-11. Interval Timer Operation Timings t Count clock TM0 Count value 0000 0001 Count start N CR00 INTTM0 TO0 Interval time Remark Interval time = ( Table 8-5. 16-Bit Timer/Event Counter Interval ...
Page 188
CHAPTER 8 16-BIT TIMER/EVENT COUNTER 8.5.2 PWM output operations By setting bits (TMC01 to 03) of the 16-bit timer mode control register (TMC0 and 0, they are operated as PWM output. Pulses with the ...
Page 189
CHAPTER 8 16-BIT TIMER/EVENT COUNTER By integrating 14-bit resolution PWM pulses with an external low-pass filter, they can be converted to an analog voltage and used for electronic tuning and D/A converter applications, etc. The analog output voltage (V ) ...
Page 190
CHAPTER 8 16-BIT TIMER/EVENT COUNTER 8.5.3 Pulse width measurement operations The pulse width of the signal to be input to theINTP0/P00/TI0 pin can be neasured with the 16-bit timer register (TM0). There are two measurement methods: measuring with TM0 used ...
Page 191
CHAPTER 8 16-BIT TIMER/EVENT COUNTER Figure 8-15. Timing of Pulse Width Measurement Operation by Free-Running Counter (with Both Edges Specified) t Count Clock TM0 Count Value 0000 0001 TI0 Pin Input CR01 Captured Value INTP0 OVF0 D0 D1 FFFF 0000 ...
Page 192
CHAPTER 8 16-BIT TIMER/EVENT COUNTER (2) Pulse width measurement by means of restart When input of a valid edge to the INTP0/P00/TI0 pin is detected, the count value of the 16-bit timer register (TM0) is taken into the 16-bit capture ...
Page 193
CHAPTER 8 16-BIT TIMER/EVENT COUNTER 8.5.4 External event counter operation The external event counter counts the number of external clock pulses to be input to the INTP0/P00/TI0 pin with the 16-bit timer register (TM0). TM0 is incremented each time the ...
Page 194
CHAPTER 8 16-BIT TIMER/EVENT COUNTER Figure 8-18. External Event Counter Operation Timings (with Rising Edge Specified) TI0 Pin Input 0000 0001 0002 0003 0004 0005 TM0 Count Value CR00 INTTM0 194 N – 0000 0001 0002 0003 N ...
Page 195
CHAPTER 8 16-BIT TIMER/EVENT COUNTER 8.5.5 Square-wave output operation The 16-bit timer/event counter operates as a square wave with any selected frequency which is output at intervals of the count value preset to the 16-bit compare register (CR00). The TO0/P30 ...
Page 196
CHAPTER 8 16-BIT TIMER/EVENT COUNTER 8.6 16-Bit Timer/Event Counter Operating Precautions (1) Timer start errors An error with a maximum of one clock may occur concerning the time required for a match signal to be generated after timer start. This ...
Page 197
CHAPTER 8 16-BIT TIMER/EVENT COUNTER (4) Capture register data retention timings If the valid edge of the TI0/P00 pin is input during 16-bit capture register (CR01) read, CR01 holds data without carrying out capture operation. However, the interrupt request flag ...
Page 198
CHAPTER 8 16-BIT TIMER/EVENT COUNTER (6) OVF0 flag operation OVF0 flag is set to 1: When clear & start mode on match between TM0 and CR00 is selected CR00 is set to FFFFH TM0 is counted up from FFFFH to ...
Page 199
CHAPTER 9 8-BIT TIMER/EVENT COUNTER CHAPTER 9 8-BIT TIMER/EVENT COUNTER 9.1 8-Bit Timer/Event Counter Functions For the 8-bit timer/event counter incorporated in the PD78014 and 78014Y Subseries, the following two modes are available. • 8-bit timer/event counter mode • 16-bit ...
Page 200
CHAPTER 9 8-BIT TIMER/EVENT COUNTER (1) 8-bit interval timer Interrupt requests are generated at the preset time intervals. Table 9-1. 8-Bit Timer/Event Counter Interval Times Minimum Interval Time 2 2 1/f (400 ns 1/f (800 ns) X ...