UPD78F9222MC(T)-5A4-A NEC, UPD78F9222MC(T)-5A4-A Datasheet
UPD78F9222MC(T)-5A4-A
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User’s Manual 78K0S/KA1+ 8-bit Single-Chip Microcontrollers µ PD78F9221 µ PD78F9221(A) µ PD78F9221(A2) Document No. U16898EJ5V0UD00 (5th edition) Date Published January 2008 NS © 2003 Printed in Japan µ PD78F9222 µ PD78F9222(A) µ PD78F9222(A2) ...
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User’s Manual U16898EJ5V0UD ...
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... IH 2 HANDLING OF UNUSED INPUT PINS Unconnected CMOS device inputs can be cause of malfunction input pin is unconnected possible that an internal input level may be generated due to noise, etc., causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using pull-up or pull-down circuitry ...
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... NEC Electronics does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC Electronics products listed in this document or any other liability arising from the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Electronics or others. • ...
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Target Readers This manual is intended for user engineers who wish to understand the functions of the 78K0S/KA1+ in order to design and develop its application systems and programs. The target devices are the following subseries products. • 78K0S/KA1+: Purpose ...
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Conventions Data significance: Active low representation: ××× (overscore over pin or signal name) Note: Caution: Remark: Numerical representation: Binary ... ×××× or ××××B Related Documents The related documents indicated in this publication may include preliminary versions. However, preliminary versions are ...
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... NEC Semiconductor Device Reliability/Quality Control System Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge (ESD) Note See the “Semiconductor Device Mount Manual” website (http://www.necel.com/pkg/en/mount/index.html). Caution The related documents listed above are subject to change without notice. Be sure to use the latest version of each document for designing ...
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... AV ...........................................................................................................................................26 REF 2.2.9 V ...............................................................................................................................................26 DD 2.2.10 V ...............................................................................................................................................26 SS 2.3 Pin I/O Circuits and Connection of Unused Pins ......................................................................26 CHAPTER 3 CPU ARCHITECTURE ......................................................................................................28 3.1 Memory Space ............................................................................................................................28 3.1.1 Internal program memory space..................................................................................................30 3.1.2 Internal data memory space ........................................................................................................30 3.1.3 Special function register (SFR) area............................................................................................31 3.1.4 Data memory addressing.............................................................................................................31 3 ...
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Stack addressing......................................................................................................................... 49 CHAPTER 4 PORT FUNCTIONS........................................................................................................... 50 4.1 Functions of Ports ..................................................................................................................... 50 4.2 Port Configuration ..................................................................................................................... 51 4.2.1 Port 2........................................................................................................................................... 52 4.2.2 Port 3........................................................................................................................................... 53 4.2.3 Port 4........................................................................................................................................... 55 4.2.4 Port 12......................................................................................................................................... 60 4.2.5 Port 13......................................................................................................................................... 62 ...
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Operation as interval timer.........................................................................................................129 7.5 Notes on 8-bit Timer 80 ...........................................................................................................131 CHAPTER 8 8-BIT TIMER H1 .............................................................................................................132 8.1 Functions of 8-bit Timer H1.....................................................................................................132 8.2 Configuration of 8-bit Timer H1 ..............................................................................................132 8.3 Registers Controlling 8-bit Timer H1 .....................................................................................135 8.4 Operation ...
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... CHAPTER 18 FLASH MEMORY..........................................................................................................265 18.1 Features ....................................................................................................................................265 18.2 Memory Configuration.............................................................................................................266 18.3 Functional Outline ...................................................................................................................267 18.4 Writing with Flash Memory Programmer...............................................................................268 18.5 Programming Environment.....................................................................................................269 18.6 Pin Connection on Board........................................................................................................271 18.6.1 X1 and X2 pins .......................................................................................................................... 271 18.6.2 RESET pin ................................................................................................................................ 272 18.6.3 Port pins .................................................................................................................................... 273 18 ...
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... CHAPTER 19 ON-CHIP DEBUG FUNCTION .......................................................................................324 19.1 Connecting QB-MINI2 to 78K0S/KA1+ ...................................................................................324 19.1.1 Connection of INTP3 pin............................................................................................................325 19.1.2 Connection of X1 and X2 pins ...................................................................................................326 19.2 Securing of user resources.....................................................................................................327 CHAPTER 20 INSTRUCTION SET OVERVIEW .................................................................................328 20.1 Operation ..................................................................................................................................328 20.1.1 Operand identifiers and description methods ............................................................................328 20.1.2 Description of “ ...
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A.5.2 When using on-chip debug emulator QB-MINI2 ........................................................................ 376 A.6 Debugging Tools (Software)...................................................................................................377 APPENDIX B NOTES ON DESIGNING TARGET SYSTEM ................................................................378 APPENDIX C REGISTER INDEX.........................................................................................................380 C.1 Register Index (Register Name) .............................................................................................380 C.2 Register Index (Symbol)..........................................................................................................382 APPENDIX D LIST OF CAUTIONS.....................................................................................................384 ...
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... O Timer: 4 channels • 16-bit timer/event counter: • 8-bit timer: • Watchdog timer: O Serial interface: UART (LIN (Local Interconnect Network) bus supported) 1 channel O 10-bit resolution A/D converter: 4 channels O On-chip power-on-clear (POC) circuit (A reset is automatically generated when the voltage drops to 2.1 V (TYP.) or below) ...
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O Enhanced development environment • Support for full-function emulator (IECUBE), simplified emulator (MINICUBE2), and simulator O Supply voltage 2 ∗ Use these products in the following voltage range because the detection voltage (V the ...
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Ordering Information Part Number PD78F9 - - µ ××× ×× (×) ××× <R> <R> <R> <R> " ...
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... Pin Configuration (Top View) • 20-pin plastic SSOP P31/TI010/TO00/INTP2 • 20-pin plastic SDIP <R> Note In the 78K0S/KA1+, V connect stabilized GND (= 0 V). SS CHAPTER 1 OVERVIEW Note P121/X1 2 P122/X2 3 P123 RESET/P34 6 7 P30/TI000/INTP0 8 P40 9 P41/INTP3 10 P23/ANI3 1 20 P22/ANI2 2 19 P21/ANI1 3 18 P20/ANI0 4 17 ...
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... REF Analog Reference Voltage, Power Supply for P20 to P23 INTP0 to INTP3: External interrupt input P20 to P23: Port 2 P30, P31, P34: Port 3 P40 to P45: Port 4 P121 to P123: Port 12 Note In the 78K0S/KA1+, V connect stabilized GND (= 0 V CHAPTER 1 OVERVIEW Top View Bottom View Name Pin No ...
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Product Lineup The following table shows the product lineup of the 78K0S/Kx1+. Part Number Item Number of pins Internal Flash memory memory RAM Supply voltage Minimum instruction execution time System clock (oscillation frequency) Clock for TMH1 and WDT ...
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... Watchdog timer RxD6/P44 Serial interface UART6 TxD6/P43 ANI0/P20 to 4 ANI3/P23 A/D converter AV REF INTP0/P30 INTP1/P43 Interrupt control INTP2/P31 INTP3/P41 Note In the 78K0S/KA1+, V connect stabilized GND (= 0 V CHAPTER 1 OVERVIEW 78K0S Flash CPU memory core Internal high-speed RAM Note functions alternately as the ground potential of the A/D converter. Be sure to SS User’ ...
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Functional Outline Item Internal Flash memory memory High-speed RAM Memory space X1 input clock (oscillation frequency) Internal High speed (oscillation oscillation frequency) clock Low speed (for TMH1 and WDT) General-purpose registers Instruction execution time I/O port Timer Timer output ...
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... I/O Port 12. 3-bit I/O port. Note P122 Can be set to input or output mode in 1-bit units. P123 An on-chip pull-up resistor can be connected only to P123 by setting software. P130 Output Port 13. 1-bit output-only port Note For the setting method for pin functions, see CHAPTER 17 OPTION BYTE. ...
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... A/D converter reference voltage input and positive power supply for P20 to P23 and A/D converter System reset input Connection of crystal/ceramic resonator for system clock oscillation. External clock input Connection of crystal/ceramic resonator for system clock oscillation. Positive power supply Ground potential User’s Manual U16898EJ5V0UD After Reset ...
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... A/D converter. These pins can be set to the following operation modes in 1-bit units. (1) Port mode P20 to P23 function as a 4-bit I/O port. Each bit of this port can be set to the input or output mode by using port mode register 2 (PM2). In addition, an on-chip pull-up resistor can be connected to the port by using pull- up resistor option register 2 (PU2). (2) Control mode P20 to P23 function as the analog input pins (ANI0 to ANI3) of the A/D converter ...
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... These pins can be set to the following operation modes in 1-bit units. (1) Port mode P40 to P45 function as a 6-bit I/O port. Each bit of this port can be set to the input or output mode by using port mode register 4 (PM4). In addition, an on-chip pull-up resistor can be connected to the port by using pull- up resistor option register 4 (PU4). (2) Control mode P40 to 45 function to output a signal from an internal timer, input external interrupt request signals, and input/output data of the serial interface ...
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... GND (= 0 V). 2.3 Pin I/O Circuits and Connection of Unused Pins Table 2-1 shows I/O circuit type of each pin and the connections of unused pins. For the configuration of the I/O circuit of each type, refer to Figure 2-1. Table 2-1. Types of Pin I/O Circuits and Connection of Unused Pins ...
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Type 2 IN Schmitt-triggered input with hysteresis characteristics Type 3-C V P-ch Data N-ch V Type 8-A Pull up enable V DD Data P-ch Output N-ch disable V SS CHAPTER 2 PIN FUNCTIONS Figure 2-1. Pin I/O Circuits Type 11 ...
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Memory Space The 78K0S/KA1+ can access memory space. Figures 3-1 and 3-2 show the memory maps Special function registers ...
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Figure 3-2. Memory Map ( PD78F9222 Special function registers Internal high-speed RAM Data memory space ...
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Internal program memory space The internal program memory space stores programs and table data. This space is usually addressed by the program counter (PC). The 78K0S/KA1+ provides the following internal ROMs (or flash memory) containing the following capacities. Part ...
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Special function register (SFR) area Special function registers (SFRs) of on-chip peripheral hardware are allocated to the area of FF00H to FFFFH (see Table 3-3). 3.1.4 Data memory addressing The 78K0S/KA1+ is provided with a wide range of addressing ...
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Figure 3-4. Data Memory Addressing ( PD78F9222 Special function registers (SFR) 256 8 bits Internal ...
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Processor Registers The 78K0S/KA1+ provides the following on-chip processor registers. 3.2.1 Control registers The control registers have special functions to control the program sequence statuses and stack memory. The control registers include a program counter, a program status word, ...
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Carry flag (CY) This flag stores overflow and underflow that have occurred upon add/subtract instruction execution. It stores the shift-out value upon rotate instruction execution and functions as a bit accumulator during bit operation instruction execution. (3) Stack pointer ...
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Figure 3-9. Data to Be Restored from Stack Memory POP rp instruction Lower half SP register pairs Upper half register pairs 3.2.2 General-purpose registers A general-purpose register consists of eight 8-bit registers (X, ...
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Figure 3-10. General-Purpose Register Configuration (2/2) 16-bit processing 15 3.2.3 Special function registers (SFRs) Unlike the general-purpose registers, each special function register has a special function. The special function registers are allocated to the 256-byte area FF00H to FFFFH. The ...
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CHAPTER 3 CPU ARCHITECTURE R/W Indicates whether the special function register can be read or written. R/W: Read/write R: Read only W: Write only Number of bits manipulated simultaneously Indicates the bit units (1, 8, and 16) in which the ...
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Table 3-3. Special Function Registers (1/2) Address Special Function Register (SFR) Name FF02H Port register 2 FF03H Port register 3 FF04H Port register 4 FF0CH Port register 12 FF0DH Port register 13 FF0EH 8-bit timer H compare register 01 FF0FH ...
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Table 3-3. Special Function Registers (2/2) Address Special Function Register (SFR) Name FF80H A/D converter mode register FF81H Analog input channel specification register FF84H Port mode control register 2 FF8CH Input switch control register FF90H Asynchronous serial interface operation mode ...
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Instruction Address Addressing An instruction address is determined by the program counter (PC) contents. The PC contents are normally incremented (+1 for each byte) automatically according to the number of bytes of an instruction to be fetched each time ...
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Immediate addressing [Function] Immediate data in the instruction word is transferred to the program counter (PC) to branch. This function is carried out when the CALL !addr16 and BR !addr16 instructions are executed. CALL !addr16 and BR !addr16 instructions ...
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Register addressing [Function] The register pair (AX) contents to be specified with an instruction word are transferred to the program counter (PC) to branch. This function is carried out when the BR AX instruction is executed. [Illustration ...
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Operand Address Addressing The following methods (addressing) are available to specify the register and memory to undergo manipulation during instruction execution. 3.4.1 Direct addressing [Function] The memory indicated by immediate data in an instruction word is directly addressed. [Operand ...
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Short direct addressing [Function] The memory to be manipulated in the fixed space is directly addressed with the 8-bit data in an instruction word. The fixed space where this addressing is applied is the 160-byte space FE80H to FF1FH ...
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Special function register (SFR) addressing [Function] A memory-mapped special function register (SFR) is addressed with the 8-bit immediate data in an instruction word. This addressing is applied to the 256-byte space FF00H to FFFFH. However, SFRs mapped at FF00H ...
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Register addressing [Function] A general-purpose register is accessed as an operand. The general-purpose register to be accessed is specified with the register specify code and functional name in the instruction code. Register addressing is carried out when an instruction ...
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Register indirect addressing [Function] The memory is addressed with the contents of the register pair specified as an operand. The register pair to be accessed is specified with the register pair specify code in the instruction code. This addressing ...
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Based addressing [Function] 8-bit immediate data is added to the contents of the base register, that is, the HL register pair, and the sum is used to address the memory. Addition is performed by expanding the offset data as ...
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Stack addressing [Function] The stack area is indirectly addressed with the stack pointer (SP) contents. This addressing method is automatically employed when the PUSH, POP, subroutine call, and return instructions are executed or the register is saved/restored upon interrupt ...
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Functions of Ports The 78K0S/KA1+ has the ports shown in Figure 4-1, which can be used for various control operations. Table 4-1 shows the functions of each port. In addition to digital I/O port functions, each of these ports ...
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... Port 12. 3-bit I/O port. Note P122 Can be set to input or output mode in 1-bit units. P123 On-chip pull-up resistor can be connected only to P123 by setting software. P130 Output Port 13. 1-bit output-only port. Note For the setting method for pin functions, see CHAPTER 17 OPTION BYTE. ...
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... Port 4-bit I/O port with an output latch. Each bit of this port can be set to the input or output mode by using port mode register 2 (PM2). When the P20 to P23 pins are used as an input port, an on-chip pull-up resistor can be connected in 1-bit units by using pull-up resistor option register 2 (PU2). This port is also used as the analog input pins of the internal A/D converter. ...
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... When the P30 to P31 pins are used as an input port, an on-chip pull-up resistor can be connected in 1-bit units by using pull-up resistor option register 3 (PU3). This port is also used for both timer I/O and external interrupt request input pin functions. ...
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WR PU PU3 PU31 Alternate function RD WR PORT P3 Output latch (P31 PM3 PM31 Alternate function P3: Port register 3 PU3: Pull-up resistor option register 3 PM3: Port mode register 3 RD: Read signal WR××: Write signal ...
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... When the P40 to P45 pins are used as an input port, an on-chip pull-up resistor can be connected in 1-bit units by using pull-up resistor option register 4 (PU4). Alternate functions include external interrupt request input, serial interface data I/O, and timer output. ...
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Figure 4-6. Block Diagram of P40 and P45 WR PU PU4 PU40, PU45 RD WR PORT P4 Output latch (P40, P45 PM4 PM40, PM45 P4: Port register 4 PU4: Pull-up resistor option register 4 PM4: Port mode register ...
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CHAPTER 4 PORT FUNCTIONS Figure 4-7. Block Diagram of P41 and P44 WR PU PU4 PU41, PU44 Alternate function RD WR PORT P4 Output latch (P41, P44 PM4 PM41, PM44 P4: Port register 4 PU4: Pull-up resistor option ...
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WR PU PU4 PU42 RD WR PORT P4 Output latch (P42 PM4 PM42 Alternate function P4: Port register 4 PU4: Pull-up resistor option register 4 PM4: Port mode register 4 RD: Read signal WR××: Write signal 58 CHAPTER ...
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CHAPTER 4 PORT FUNCTIONS Figure 4-9. Block Diagram of P43 WR PU PU4 PU43 Alternate function RD WR PORT P4 Output latch (P43 PM4 PM43 Alternate function P4: Port register 4 PU4: Pull-up resistor option register 4 PM4: ...
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... When the P123 pin is used as an input port, an on-chip pull-up resistor can be connected by using pull-up resistor option register 12 (PU12). The P121 and P122 pins are also used as the X1 and X2 pins of the system clock oscillator. The functions of the P121 and P122 pins differ, therefore, depending on the selected system clock oscillator ...
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CHAPTER 4 PORT FUNCTIONS Figure 4-11. Block Diagram of P123 WR PU PU12 PU123 RD WR PORT P12 Output latch (P123 PM12 PM123 P12: Port register 12 PU12: Pull-up resistor option register 12 PM12: Port mode register 12 ...
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Port 13 This is a 1-bit output-only port. Figure 4-12 shows the block diagram of port 13 PORT Output latch (P130) P13: Port register 13 RD: Read signal WR××: Write signal Remark When a reset is input, ...
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... Port registers (P2, P3, P4, P12, P13) These registers are used to write data to be output from the corresponding port pin to an external device connected to the chip. When a port register is read, the pin level is read in the input mode, and the value of the output latch of the port is read in the output mode ...
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Address: FF02H After reset: 00H (Output latch) R/W Symbol Note Address: FF03H After reset: 00H (Output latch) R/W Symbol Address: FF04H After reset: 00H (Output latch) R/W Symbol 7 6 ...
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Figure 4-15. Format of Port Mode Control Register 2 Address: FF84H After reset: 00H R/W Symbol 7 6 PMC2 0 0 PMC2n 0 Port mode 1 A/D converter mode Caution When PMC20 to PMC23 are set to 1, the P20/ANI0 ...
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... Address: FF34H After reset: 00H R/W Symbol 7 6 PU4 0 0 Address: FF3CH After reset: 00H R/W Symbol 7 6 PU12 0 0 PUmn Selection of connection of on-chip pull-up resistor of Pmn ( 12 Does not connect on-chip pull-up resistor 1 Connects on-chip pull-up resistor 66 CHAPTER 4 PORT FUNCTIONS PU23 5 4 ...
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Operation of Port Function The operation of a port differs, as follows, depending on the setting of the I/O mode. Caution Although a 1-bit memory manipulation instruction manipulates 1 bit, it accesses a port in 8-bit units. Therefore, the ...
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... If the high-speed internal oscillator is selected to supply the system clock, the X1 and X2 pins can be used as I/O port pins. • Crystal/ceramic oscillator This circuit oscillates a clock with a crystal/ceramic oscillator connected across the X1 and X2 pins. It can oscillate a clock MHz. Oscillation of this circuit can be stopped by execution of the STOP instruction. • External clock input circuit This circuit supplies a clock from an external IC to the X1 pin ...
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Configuration of Clock Generators The clock generators consist of the following hardware. Table 5-1. Configuration of Clock Generators Item Control registers Processor clock control register (PCC) Preprocessor clock control register (PPCC) Low-speed internal oscillation mode register (LSRCM) Oscillation stabilization ...
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Figure 5-1. Block Diagram of Clock Generators Oscillation stabilization time select register (OSTS) OSTS1 OSTS0 System clock oscillation stabilization time counter STOP Watchdog timer System clock Note oscillator X1/P121 Crystal/ceramic oscillation X2/P122 X 2 External clock input ...
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Registers Controlling Clock Generators The clock generators are controlled by the following four registers. • Processor clock control register (PCC) • Preprocessor clock control register (PPCC) • Low-speed internal oscillation mode register (LSRCM) • Oscillation stabilization time select register ...
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The fastest instruction of the 78K0S/KA1+ is executed in two CPU clocks. Therefore, the relationship between the CPU clock (f ) and the minimum instruction execution time is as shown in Table 5-2. CPU Table 5-2. Relationship Between CPU Clock ...
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Oscillation stabilization time select register (OSTS) This register is used to select oscillation stabilization time of the clock supplied from the oscillator when the STOP mode is released. The wait time set by OSTS is valid only when the ...
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... For details of the option byte, refer to CHAPTER 17 OPTION BYTE. For details of I/O ports, refer to CHAPTER 4 PORT FUNCTIONS. 5.4.2 Crystal/ceramic oscillator The crystal/ceramic oscillator oscillates using a crystal or ceramic resonator connected between the X1 and X2 pins. If the crystal/ceramic oscillator is selected by the option byte as the system clock source, the X1 and X2 pins are used as crystal or ceramic resonator connection pins. ...
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... Figure 5-7 shows examples of incorrect resonator connection. Figure 5-7. Examples of Incorrect Resonator Connection (1/2) (a) Too long wiring of connected circuit (c) Wiring near high fluctuating current CHAPTER 5 CLOCK GENERATORS (b) Crossed signal lines V (d) Current flowing through ground line of oscillator (Potential at points A, B, and C fluctuates.) ...
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... Figure 5-7. Examples of Incorrect Resonator Connection (2/2) (e) Signals are fetched 5.4.3 External clock input circuit This circuit supplies a clock from an external IC to the X1 pin. If external clock input is selected by the option byte as the system clock source, the X2 pin can be used as an I/O port pin ...
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Operation of CPU Clock Generator A clock ( supplied to the CPU from the system clock (f CPU oscillators. • High-speed internal oscillator: • Crystal/ceramic oscillator: • External clock input circuit: The system clock oscillator is selected ...
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The internal reset signal is generated by the power-on-clear function on power application, the option byte is referenced after reset, and the system clock is selected. (b) The option byte is referenced and the system clock is selected. Then ...
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Figure 5-10. Timing Chart of Default Start by Crystal/Ceramic Oscillator ( RESET H Internal reset System clock CPU clock System clock is selected. (Operation stops Notes 1. Operation stop time is 276 2. The clock oscillation stabilization time ...
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Figure 5-11. Status Transition of Default Start by Crystal/Ceramic Oscillation Interrupt HALT Remark PCC: Processor clock control register PPCC: Preprocessor clock control register (3) External clock input circuit If external clock input is selected by the option byte, the following ...
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CHAPTER 5 CLOCK GENERATORS Figure 5-12. Timing of Default Start by External Clock Input ( RESET H Internal reset System clock CPU clock Option byte is read. System clock is selected. (Operation stops µ Note Operation stop time ...
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Operation of Clock Generator Supplying Clock to Peripheral Hardware The following two types of clocks are supplied to the peripheral hardware. • Clock to peripheral hardware (f XP • Low-speed internal oscillation clock (f (1) Clock to peripheral hardware ...
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Figure 5-14. Status Transition of Low-Speed Internal Oscillation Can be stopped Clock source of WDT is selected Note by software Low-speed internal oscillator can be stopped LSRSTOP = 1 Low-speed internal oscillator stops Note The clock source of the watchdog ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 6.1 Functions of 16-bit Timer/Event Counter 00 16-bit timer/event counter 00 has the following functions. (1) Interval timer 16-bit timer/event counter 00 generates interrupt requests at the preset time interval. • Number of counts: ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 6.2 Configuration of 16-bit Timer/Event Counter 00 16-bit timer/event counter 00 consists of the following hardware. Table 6-1. Configuration of 16-bit Timer/Event Counter 00 Item Timer counter Register Timer input Timer output Control registers ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 (1) 16-bit timer counter 00 (TM00) TM00 is a 16-bit read-only register that counts count pulses. The counter is incremented in synchronization with the rising edge of the count clock. If the count value ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Table 6-2. CR000 Capture Trigger and Valid Edges of TI000 and TI010 Pins (1) TI000 pin valid edge selected as capture trigger (CRC001 = 1, CRC000 = 1) CR000 Capture Trigger Falling edge Rising ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 (3) 16-bit capture/compare register 010 (CR010) CR010 is a 16-bit register which has the functions of both a capture register and a compare register. Whether it is used as a capture register or a ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 6.3 Registers to Control 16-bit Timer/Event Counter 00 The following six types of registers are used to control 16-bit timer/event counter 00. • 16-bit timer mode control register 00 (TMC00) • Capture/compare control register ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-5. Format of 16-bit Timer Mode Control Register 00 (TMC00) Address: FF60H After reset: 00H R/W Symbol TMC00 TMC003 TMC003 TMC002 TMC001 Operating mode ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 (2) Capture/compare control register 00 (CRC00) This register controls the operation of the 16-bit capture/compare registers (CR000, CR010). CRC00 is set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets the ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 (3) 16-bit timer output control register 00 (TOC00) This register controls the operation of the 16-bit timer/event counter output controller. It sets timer output F/F set/reset, output inversion enable/disable, 16-bit timer/event counter 00 timer ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 (4) Prescaler mode register 00 (PRM00) This register is used to set the 16-bit timer counter 00 (TM00) count clock and the TI000, TI010 pin input valid edges. PRM00 is set by a 1-bit ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Cautions 1. Always set data to PRM00 after stopping the timer operation the valid edge of the TI000 pin set as the count clock, do not set the clear/start ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 6.4 Operation of 16-bit Timer/Event Counter 00 6.4.1 Interval timer operation Setting 16-bit timer mode control register 00 (TMC00) and capture/compare control register 00 (CRC00) as shown in Figure 6-10 allows operation as an ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-10. Control Register Settings for Interval Timer Operation (a) Capture/compare control register 00 (CRC00 CRC00 ES110 ES100 ES010 ES000 PRM00 0/1 0/1 0/1 0/1 (c) ...
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... TM00 continues counting, overflows and then restarts counting from 0. Thus, if the value (M) after the CR000 change is smaller than that (N) before the change necessary to restart the timer after changing CR000. Figure 6-13. Timing After Change of Compare Register During Timer Count Operation (N → > M) ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 The external event counter counts the number of external clock pulses to be input to the TI000 pin with using 16-bit timer counter 00 (TM00). TM00 is incremented each time the valid edge specified ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-15. External Event Counter Configuration Diagram f Noise eliminator XP Valid edge of TI000 Note OVF00 is 1 only when 16-bit timer capture/compare register 000 is set to FFFFH. Figure 6-16. External Event ...
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... When an interrupt occurs, read the valid value of the capture register, check the overflow flag, and then calculate the necessary pulse width. Clear the overflow flag after checking it. The capture operation is not performed until the signal pulse width is sampled in the count clock cycle selected by prescaler mode register 00 (PRM00) and the valid level of the TI000 or TI010 pin is detected twice, thus eliminating noise with a short pulse width ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 (1) Pulse width measurement with free-running counter and one capture register Specify both the rising and falling edges as the valid edges of the TI000 pin, by using bits 4 and 5 (ES000 and ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-19. Configuration Diagram for Pulse Width Measurement by Free-Running Counter TI000/INTP0/P30 Figure 6-20. Timing of Pulse Width Measurement Operation by Free-Running Counter and ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Caution The measurable pulse width in this operation example cycle of the timer counter. Figure 6-21. Control Register Settings for Measurement of Two Pulse Widths with Free-Running Counter (a) Capture/compare ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-22. Timing of Pulse Width Measurement Operation with Free-Running Counter (with Both Edges Specified) t Count clock 0000H 0001H TM00 count value TI000 pin input CR010 capture value INTTM010 TI010 pin input CR000 ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-23. Control Register Settings for Pulse Width Measurement with Free-Running Counter and Two Capture Registers (with Rising Edge Specified) (a) Capture/compare control register 00 (CRC00 CRC00 (b) ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-24. Timing of Pulse Width Measurement Operation by Free-Running Counter and Two Capture Registers (with Rising Edge Specified) t Count clock TM00 count value 0000H 0001H TI000 pin input CR010 capture value CR000 ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-25. Control Register Settings for Pulse Width Measurement by Means of Restart (b) Prescaler mode register 00 (PRM00) ES110 ES100 ES010 ES000 PRM00 0/1 0 (c) 16-bit timer mode control register ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 6.4.4 Square-wave output operation Setting The basic operation setting procedure is as follows. <1> Set the count clock by using the PRM00 register. <2> Set the CRC00 register (see Figure 6-27 for the set ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-27. Control Register Settings in Square-Wave Output Mode (2/2) (c) 16-bit timer output control register 00 (TOC00) 7 OSPT00 OSPE00 TOC004 LVS00 TOC00 0/1 (d) 16-bit timer mode control ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 6.4.5 PPG output operations Setting 16-bit timer mode control register 00 (TMC00) and capture/compare control register 00 (CRC00) as shown in Figure 6-29 allows operation as PPG (Programmable Pulse Generator) output. Setting The basic ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-29. Control Register Settings for PPG Output Operation (a) Capture/compare control register 00 (CRC00 CRC00 (b) 16-bit timer output control register 00 (TOC00) 7 OSPT00 ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-30. Configuration Diagram of PPG Output Noise TI000/INTP0/P30 eliminator f XP Figure 6-31. PPG Output Operation Timing Count clock TM00 count value N ...
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... Set the TMC00 register to start the operation (see Figures 6-32 and 6-34 for the set value). Remarks 1. For the setting of the TO00 pin, see 6.3 (5) Port mode register 3 (PM3). 2. For how to enable the INTTM000 (if necessary, INTTM010) interrupt, see CHAPTER 12 INTERRUPT FUNCTIONS. ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-32. Control Register Settings for One-Shot Pulse Output with Software Trigger ES110 ES100 ES010 PRM00 0/1 0/1 0/1 (b) Capture/compare control register 00 (CRC00 CRC00 (c) 16-bit ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-33. Timing of One-Shot Pulse Output Operation with Software Trigger Set TMC00 to 04H (TM00 count starts) Count clock TM00 count 0000H 0001H CR010 set value N CR000 set value M OSPT00 INTTM010 ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-34. Control Register Settings for One-Shot Pulse Output with External Trigger ES110 ES100 ES010 PRM00 0/1 0/1 0 (b) Capture/compare control register 00 (CRC00 CRC00 (c) 16-bit ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-35. Timing of One-Shot Pulse Output Operation with External Trigger (with Rising Edge Specified) When TMC00 is set to 08H (TM00 count starts) t Count clock TM00 count value 0000H 0001H CR010 set ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 6.5 Cautions Related to 16-bit Timer/Event Counter 00 (1) Timer start errors An error one clock may occur in the time required for a match signal to be generated after timer ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 (4) Capture register data retention The value of 16-bit timer capture/compare register 0n0 (CR0n0) after 16-bit timer/event counter 00 has stopped is not guaranteed. Remark (5) Setting of 16-bit timer ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 (12) One-shot pulse output with external trigger <1> Do not input the external trigger again while the one-shot pulse is output. To output the one-shot pulse again, wait until the current one-shot pulse output ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 (14) Conflicting operations If the register read period and the input of the capture trigger conflict when CR000/CR010 is used as a capture register, the capture trigger input takes precedence and the read data ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 (17) Changing compare register during timer operation <1> With the 16-bit timer capture/compare register 0n0 (CR0n0) used as a compare register, when changing CR0n0 around the timing of a match between 16-bit timer counter ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 (18) Edge detection <1> In the following cases, note with caution that the valid edge of the TI0n0 pin is detected. (a) Immediately after a system reset high level is input to ...
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CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 (23) External clock limitation <1> When using an input pulse of the TI000 pin as a count clock (external trigger), be sure to input the pulse width which satisfies the AC characteristics. For the ...
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Function of 8-bit Timer 80 8-bit timer 80 has an 8-bit interval timer function and generates an interrupt at intervals specified in advance. Minimum Interval Time 8.0 MHz ...
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Configuration of 8-bit Timer 80 8-bit timer 80 consists of the following hardware. Table 7-2. Configuration of 8-bit Timer 80 Item Timer counter 8-bit timer counter 80 (TM80) Register 8-bit compare register 80 (CR80) Control register 8-bit timer mode ...
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This 8-bit register always compares its set value with the count value of 8-bit timer/counter 80 (TM80). It generates an interrupt request signal (INTTM80) if the two values match. CR80 is set by using ...
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Register Controlling 8-bit Timer 80 8-bit timer 80 is controlled by 8-bit timer mode control register 80 (TMC80). (1) 8-bit timer mode control register 80 (TMC80) This register is used to enable or stop the operation of 8-bit timer/counter ...
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Operation of 8-bit Timer 80 7.4.1 Operation as interval timer When 8-bit timer 80 operates as an interval timer, it can repeatedly generate an interrupt at intervals specified by the count value set in advance to 8-bit compare register ...
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Figure 7-5. Timing of Interval Timer Operation t Count clock TM80 count value 00H 01H CR80 N TCE80 Count start INTTM80 Remark Interval time = ( × 00H to FFH 130 CHAPTER 7 8-BIT TIMER ...
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Notes on 8-bit Timer 80 (1) Error when timer starts The time from starting the timer to generation of the match signal includes an error 1.5 clocks. This is because, if the timer is started while ...
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Functions of 8-bit Timer H1 8-bit timer H1 has the following functions. • Interval timer • PWM output mode • Square-wave output 8.2 Configuration of 8-bit Timer H1 8-bit timer H1 consists of the following hardware. Item Timer register ...
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H mode register 1 (TMHMD1) TMHE1 CKS12 CKS11 CKS10 TMMD11 TMMD10 TOLEV1 TOEN1 3 2 Decoder ...
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H compare register 01 (CMP01) This register can be read or written by an 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H. Figure 8-2. Format of 8-bit Timer H Compare Register 01 (CMP01) ...
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Registers Controlling 8-bit Timer H1 The following three registers are used to control 8-bit timer H1. • 8-bit timer H mode register 1 (TMHMD1) • Port mode register 4 (PM4) • Port register 4 (P4) (1) 8-bit timer H ...
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Figure 8-4. Format of 8-bit Timer H Mode Register 1 (TMHMD1) Address: FF70H After reset: 00H <7> Symbol TMHMD1 TMHE1 TMHE1 0 Stop timer count operation (counter is cleared Enable timer count operation (count operation started by ...
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Port mode register 4 (PM4) This register sets port 4 input/output in 1-bit units. When using the P42/TOH1 pin for timer output, clear PM42 and the output latch of P42 to 0. PM4 can be set by a 1-bit ...
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Operation of 8-bit Timer H1 8.4.1 Operation as interval timer/square-wave output When 8-bit timer counter H1 and compare register 01 (CMP01) match, an interrupt request signal (INTTMH1) is generated and 8-bit timer counter H1 is cleared to 00H. Compare ...
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Timing chart The timing of the interval timer/square-wave output operation is shown below. Figure 8-7. Timing of Interval Timer/Square-Wave Output Operation (1/2) (a) Basic operation (01H ≤ CMP01 ≤ FEH) Count clock Count start 00H 01H 8-bit timer counter ...
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Figure 8-7. Timing of Interval Timer/Square-Wave Output Operation (2/2) Count clock Count start 00H 01H 8-bit timer counter H1 CMP01 TMHE1 INTTMH1 TOH1 Count clock Count start 8-bit timer counter H1 CMP01 TMHE1 INTTMH1 TOH1 Interval time 140 CHAPTER 8 ...
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Operation as PWM output mode In PWM output mode, a pulse with an arbitrary duty and arbitrary cycle can be output. 8-bit timer compare register 01 (CMP01) controls the cycle of timer output (TOH1). Rewriting the CMP01 register during ...
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When 8-bit timer counter H1 and the CMP11 register match, TOH1 output becomes inactive and the compare register to be compared with 8-bit timer counter H1 is changed from the CMP11 register to the CMP01 register. At this time, ...
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Timing chart The operation timing in PWM output mode is shown below. Caution Make sure that the CMP11 register setting value (M) and CMP01 register setting value (N) are within the following range. 00H ≤ CMP11 (M) < CMP01 ...
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Figure 8-9. Operation Timing in PWM Output Mode (2/4) (b) Operation when CMP01 = FFH, CMP11 = 00H Count clock 8-bit timer counter H1 00H 01H CMP01 CMP11 TMHE1 INTTMH1 TOH1 (TOLEV1 = 0) (c) Operation when CMP01 = FFH, ...
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CHAPTER 8 8-BIT TIMER H1 Figure 8-9. Operation Timing in PWM Output Mode (3/4) (d) Operation when CMP01 = 01H, CMP11 = 00H Count clock 00H 01H 00H 01H 00H 8-bit timer counter H1 CMP01 CMP11 TMHE1 INTTMH1 TOH1 (TOLEV1 ...
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Figure 8-9. Operation Timing in PWM Output Mode (4/4) (e) Operation by changing CMP11 (CMP11 = 02H → 03H, CMP01 = A5H) Count clock 00H 01H 02H 8-bit timer counter H1 CMP01 02H CMP11 TMHE1 INTTMH1 TOH1 (TOLEV1 = 0) ...
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Functions of Watchdog Timer The watchdog timer is used to detect an inadvertent program loop program loop is detected, an internal reset signal is generated. When a reset occurs due to the watchdog timer, bit 4 (WDTRF) ...
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Table 9-2. Option Byte Setting and Watchdog Timer Operation Mode Low-Speed Internal Oscillator Cannot Be Stopped Low-Speed Internal Oscillator Can Be Stopped by Software Note 1 Watchdog timer clock Fixed source Operation after reset Operation starts ...
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Configuration of Watchdog Timer The watchdog timer consists of the following hardware. Table 9-3. Configuration of Watchdog Timer Item Control registers Figure 9-1. Block Diagram of Watchdog Timer 2 Clock 16-bit input counter ...
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Registers Controlling Watchdog Timer The watchdog timer is controlled by the following two registers. • Watchdog timer mode register (WDTM) • Watchdog timer enable register (WDTE) (1) Watchdog timer mode register (WDTM) This register sets the overflow time and ...
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Cautions 1. Set bits 7, 6, and and 1, respectively. Do not set the other values. 2. After reset is released, WDTM can be written only once by an 8-bit memory manipulation instruction. If writing is ...
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Operation of Watchdog Timer 9.4.1 Watchdog timer operation when “low-speed internal oscillator cannot be stopped” is selected by option byte The operation clock of watchdog timer is fixed to low-speed internal oscillation clock. After reset is released, operation is ...
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CHAPTER 9 WATCHDOG TIMER Figure 9-4. Status Transition Diagram When “Low-Speed Internal Oscillator Cannot Be Stopped” Is Selected by Option Byte WDT clock: f Overflow time: 546.13 ms (MAX.) WDTE = “ACH” Clear WDT counter. WDT clock: f Overflow time: ...
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Watchdog timer operation when “low-speed internal oscillator can be stopped by software” is selected by option byte The operation clock of the watchdog timer can be selected as either the low-speed internal oscillation clock or the system clock. After ...
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Figure 9-5. Status Transition Diagram When “Low-Speed Internal Oscillator Can Be Stopped by Software” Is Selected by Option Byte WDT clock = f X Select overflow time (settable only once). WDTE = “ACH” Clear WDT counter. WDT clock ...
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Watchdog timer operation in STOP mode (when “low-speed internal oscillator can be stopped by software” is selected by option byte) The watchdog timer stops counting during STOP instruction execution regardless of whether the system clock or low-speed internal oscillation ...
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When the watchdog timer operation clock is the low-speed internal oscillation clock (f instruction is executed When the STOP instruction is executed, operation of the watchdog timer is stopped. After STOP mode is µ released, operation stops for 34 ...
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Watchdog timer operation in HALT mode (when “low-speed internal oscillator can be stopped by software” is selected by option byte) The watchdog timer stops counting during HALT instruction execution regardless of whether the operation clock of the watchdog timer ...
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Functions of A/D Converter The A/D converter converts an analog input signal into a digital value, and consists four channels (ANI0 to ANI3) with a resolution of 10 bits. The A/D converter has the following function. ...
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Reference Sampling Note 2 Voltage Time Note 1 Range AV ≥ 4.5 V 12/f REF XP ≥ 4 24/f REF XP AV ≥ 2.85 V 96/f REF XP 48/f XP 48/f XP 24/f XP ≥ 2 ...
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... The sample & hold circuit samples the input signal of the analog input pin selected by the selector when A/D conversion is started, and holds the sampled analog input voltage value during A/D conversion. (3) D/A converter The D/A converter is connected between AV analog input signal. (4) Voltage comparator The voltage comparator compares the sampled analog input voltage and the output voltage of the D/A converter ...
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... SS (10) V pin SS This is the ground potential pin. In the 78K0S/KA1+, V functions alternately as the ground potential of the A/D converter. Be sure to connect stabilized GND (= 0 V). SS (11) A/D converter mode register (ADM) This register is used to set the conversion time of the analog input signal to be converted, and to start or stop the conversion operation ...
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Registers Used by A/D Converter The A/D converter uses the following six registers. • A/D converter mode register (ADM) • Analog input channel specification register (ADS) • 10-bit A/D conversion result register (ADCR) • 8-bit A/D conversion result register ...
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A/D converter mode register (ADM) This register sets the conversion time for analog input to be A/D converted, and starts/stops conversion. ADM can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears this register ...
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Notes 2. Be sure to set the FR2, FR1, and FR0, in accordance with the reference voltage so that Notes 2 and 3 below are satisfied. Example When AV 3. Set the sampling time as follows. • AV REF • ...
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Cautions bit other than ADCS of ADM is manipulated while A/D conversion is stopped (ADCS = 0) and then A/D conversion is started, execute two NOP instructions or an instruction equivalent to two machine cycles, and set ...
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A/D conversion result register (ADCRH) This register is an 8-bit register that stores the A/D conversion result. It stores the higher 8 bits of a 10-bit resolution result. ADCRH can be read by an 8-bit memory manipulation instruction. ...
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A/D Converter Operations 10.4.1 Basic operations of A/D converter <1> Set ADCE to 1. <2> Select one channel for A/D conversion using the analog input channel specification register (ADS), and select the conversion time using FR2 to FR0. <3> ...
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Figure 10-10. Basic Operation of A/D Converter Sampling time A/D converter Sampling operation Undefined SAR ADCR, ADCRH INTAD A/D conversion operations are performed continuously until bit 7 (ADCS) of the A/D converter mode register (ADM) is reset (0) by software. ...
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Input voltage and conversion results The relationship between the analog input voltage input to the analog input pins (ANI0 to ANI3) and the theoretical A/D conversion result (stored in the 10-bit A/D conversion result register (ADCR)) is shown by ...
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A/D converter operation mode The operation mode of the A/D converter is the select mode. One channel of analog input is selected from ANI0 to ANI3 by the analog input channel specification register (ADS) and A/D conversion is executed. ...
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The setting method is described below. <1> Set bit 0 (ADCE) of the A/D converter mode register (ADM <2> Select the channel and conversion time using bits 1 and 0 (ADS1, ADS0) of the analog input channel specification ...
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How to Read A/D Converter Characteristics Table Here, special terms unique to the A/D converter are explained. (1) Resolution This is the minimum analog input voltage that can be identified. That is, the percentage of the analog input voltage ...
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Full-scale error This shows the difference between the actual measurement value of the analog input voltage and the theoretical value (Full-scale − 3/2LSB) when the digital output changes from 1......110 to 1......111. (6) Integral linearity error This shows the ...
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Cautions for A/D Converter (1) Operating current in STOP mode To satisfy the DC characteristics of the supply current in the STOP mode, clear bit 7 (ADCS) and bit 0 (ADCE) of the A/D converter mode register (ADM) to ...
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... Noise countermeasures To maintain the 10-bit resolution, attention must be paid to noise input to the AV <1> Connect a capacitor with a low equivalent resistance and a high frequency response to the power supply. <2> Because the effect increases in proportion to the output impedance of the analog input source recommended that a capacitor be connected externally, as shown in Figure 9-19, to reduce noise. ...
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Interrupt request flag (ADIF) The interrupt request flag (ADIF) is not cleared even if the analog input channel specification register (ADS) is changed. Therefore analog input pin is changed during A/D conversion, the A/D conversion result and ...
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Operating current at conversion waiting mode The DC characteristic of the operating current during the STOP mode is not satisfied due to the conversion waiting mode (only the comparator consumes power), when bit 7 (ADCS) and bit 0 (ADCE) ...
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... For details, see 11.4.1 Operation stop mode. (2) Asynchronous serial interface (UART) mode This mode supports the LIN (Local Interconnect Network)-bus. The functions of this mode are outlined below. For details, see 11.4.2 Asynchronous serial interface (UART) mode and 11.4.3 generator. ...
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... LIN master via the LIN network. Normally, the LIN master is connected to a network such as CAN (Controller Area Network). In addition, the LIN bus uses a single-wire method and is connected to the nodes via a transceiver that complies with ISO9141. In the LIN protocol, the master transmits a frame with baud rate information and the slave receives it and corrects the baud rate error. Therefore, communication is possible when the baud rate error in the slave is ± ...
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... The input signal of the reception port input (RxD6) can be input to the external interrupt (INTP0) and 16-bit timer/event counter 00 by port input switch control (ISC0/ISC1), without connecting RxD6 and INTP0/TI000 externally. CHAPTER 11 SERIAL INTERFACE UART6 Figure 11-2 ...
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Figure 11-3. Port Configuration for LIN Reception Operation P44 Output latch P30/INTP0/TI000 Output latch Remark ISC0, ISC1: Bits 0 and 1 of the input switch control register (ISC) (see Figure 11-11) The peripheral functions used in the LIN ...
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Configuration of Serial Interface UART6 Serial interface UART6 consists of the following hardware. Table 11-1. Configuration of Serial Interface UART6 Item Registers Receive buffer register 6 (RXB6) Receive shift register 6 (RXS6) Transmit buffer register 6 (TXB6) Transmit shift ...
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Asynchronous serial interface operation mode register 6 (ASIM6 XCLK6 XP 5 (Base clock ...
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Receive buffer register 6 (RXB6) This 8-bit register stores parallel data converted by receive shift register 6 (RXS6). Each time 1 byte of data has been received, new receive data is transferred to this register from receive shift register ...
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Registers Controlling Serial Interface UART6 Serial interface UART6 is controlled by the following nine registers. • Asynchronous serial interface operation mode register 6 (ASIM6) • Asynchronous serial interface reception error status register 6 (ASIS6) • Asynchronous serial interface transmission ...
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CHAPTER 11 SERIAL INTERFACE UART6 Figure 11-5. Format of Asynchronous Serial Interface Operation Mode Register 6 (ASIM6) (2/2) Note 1 TXE6 0 Disable transmission (synchronously reset the transmission circuit). 1 Enable transmission Note 2 RXE6 0 Disable reception (synchronously reset ...
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Cautions 2. At startup, reception enable status is entered by setting RXE6 to 1 after having set POWER6 to 1 and one clock of the base clock (f operation, set POWER6 to 0 after having set RXE6 ...
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Asynchronous serial interface transmission status register 6 (ASIF6) This register indicates the status of transmission by serial interface UART6. It includes two status flag bits (TXBF6 and TXSF6). Transmission can be continued without disruption even during an interrupt period, ...
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Clock selection register 6 (CKSR6) This register selects the base clock of serial interface UART6. CKSR6 can be set by an 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H. Remark CKSR6 can be refreshed (the ...
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Baud rate generator control register 6 (BRGC6) This register sets the division value of the 8-bit counter of serial interface UART6. BRGC6 can be set by an 8-bit memory manipulation instruction. Reset signal generation sets this register to FFH. ...
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Asynchronous serial interface control register 6 (ASICL6) This register controls the serial communication operations of serial interface UART6. ASICL6 can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets this register to 16H. Caution ...
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CHAPTER 11 SERIAL INTERFACE UART6 Figure 11-10. Format of Asynchronous Serial Interface Control Register 6 (ASICL6) (2/2) SBL62 SBL61 DIR6 0 MSB 1 LSB ...
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... Input switch control register (ISC) The input switch control register (ISC) is used to receive a status signal transmitted from the master during LIN (Local Interconnect Network) reception. By setting 1 to ISC0 and ISC1, the input source to INTP0 and TI000 switches to the input signal from the P44/RxD6 pin ...
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Operation of Serial Interface UART6 Serial interface UART6 has the following two modes. • Operation stop mode • Asynchronous serial interface (UART) mode 11.4.1 Operation stop mode In this mode, serial communication cannot be executed; therefore, the power consumption ...
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Asynchronous serial interface (UART) mode In this mode, data of 1 byte is transmitted/received following a start bit, and a full-duplex operation can be performed. A dedicated UART baud rate generator is incorporated, so that communication can be executed ...
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The relationship between the register settings and pins is shown below. Table 11-2. Relationship Between Register Settings and Pins POWER6 TXE6 RXE6 PM43 Note × Note × Note ...
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Communication operation (a) Format and waveform example of normal transmit/receive data Figures 11-13 and 11-14 show the format and waveform example of the normal transmit/receive data. Figure 11-13. Format of Normal UART Transmit/Receive Data 1. LSB-first transmission/reception Start D0 ...
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CHAPTER 11 SERIAL INTERFACE UART6 Figure 11-14. Example of Normal UART Transmit/Receive Data Waveform 1. Data length: 8 bits, LSB first, Parity: Even parity, Stop bit: 1 bit, Communication data: 55H Start Data length: 8 bits, ...
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Parity types and operation The parity bit is used to detect a bit error in communication data. Usually, the same type of parity bit is used on both the transmission and reception sides. With even parity and odd parity, ...