UPD78F9222MC(T)-5A4-A NEC, UPD78F9222MC(T)-5A4-A Datasheet - Page 281

• Manufacturer Part Number: UPD78F9222MC(T)-5A4-A
• Description: 8BIT MCU, 4K FLASH, 256B RAM, 78F9222
• Manufacturer: NEC

Specifications of UPD78F9222MC(T)-5A4-A

• Controller Family/series: UPD78
• No. Of I/o's: 17
• Ram Memory Size: 256Byte
• Cpu Speed: 10MHz
• No. Of Timers: 4
• No. Of: RoHS Compliant
• Core Size: 8bit
• Program Memory Size: 4KB
• Oscillator Type: External, Internal

(3) Flash status register (PFS)
1. Operating conditions of FPRERR flag
<Setting conditions>
• If PFCMD is written when the store instruction operation recently performed on a peripheral register is not to
• If the first store instruction operation after <1> is on a peripheral register other than FLPMC
• If the first store instruction operation after <2> is on a peripheral register other than FLPMC
Caution Interrupt servicing cannot be executed in self programming mode.
Caution Check FPRERR using a 1-bit memory manipulation instruction.
<3> Write the inverted value of the value to be set to bit 0 (FLSPM) of the FLPMC (writing in this step is
<4> Write the value to be set to bit 0 (FLSPM) of the FLPMC (writing in this step is valid)
This rewrites the value of the register, so that the register cannot be written illegally.
Occurrence of an illegal write operation can be checked by bit 0 (FPRERR) of the flash status register (PFS).
Check FPRERR using a 1-bit memory manipulation instruction.
A5H must be written to PFCMD each time the value of FLPMC is changed.
PFCMD can be set with an 8-bit memory manipulation instruction.
Reset signal generation makes PFCMD undefined.
If data is not written to the flash programming mode control register (FLPMC), which is protected, in the correct
sequence (writing the flash protect command register (PFCMD)), FLPMC is not written and a protection error
occurs. If this happens, bit 0 of PFS (FPRERR) is set to 1.
When FPRERR is 1, it can be cleared to 0 by writing 0 to it.
Errors that may occur during self programming are reflected in bit 1 (VCERR) and bit 2 (WEPRERR) of PFS.
VCERR or WEPRERR can be cleared by writing 0 to them.
All the flags of the PFS register must be pre-cleared to 0 to check if the operation is performed correctly.
PFS can be set with a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears PFS to 00H.
write a specific value (A5H) to FLPMC
Address: FFA0H
Address: FFA1H
PFCMD
invalid)
Symbol
Symbol
PFS
servicing (by executing the DI instruction while MK0 and MK1 = FFH) between the points
before executing the specific sequence that sets self programming mode and after executing
the specific sequence that changes the mode to the normal mode.
Figure 18-11. Format of Flash Protect Command Register (PFCMD)
REG7
7
7
0
Figure 18-12. Format of Flash Status Register (PFS)
After reset: Undefined
After reset: 00H
REG6
0
6
6
CHAPTER 18 FLASH MEMORY
REG5
User’s Manual U16898EJ5V0UD
0
5
5
R/W
REG4
W
4
4
0
REG3
3
3
0
WEPRERR
REG2
2
2
VCERR
REG1
1
1
FPRERR
REG0
Disable interrupt
0
0
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