UPD78F9222MC(T)-5A4-A NEC, UPD78F9222MC(T)-5A4-A Datasheet - Page 175
UPD78F9222MC(T)-5A4-A
Manufacturer Part Number
UPD78F9222MC(T)-5A4-A
Description
8BIT MCU, 4K FLASH, 256B RAM, 78F9222
Manufacturer
NEC
Datasheet
1.UPD78F9222MCT-5A4-A.pdf
(414 pages)
Specifications of UPD78F9222MC(T)-5A4-A
Controller Family/series
UPD78
No. Of I/o's
17
Ram Memory Size
256Byte
Cpu Speed
10MHz
No. Of Timers
4
No. Of
RoHS Compliant
Core Size
8bit
Program Memory Size
4KB
Oscillator Type
External, Internal
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10.6 Cautions for A/D Converter
(1) Operating current in STOP mode
(2) Input range of ANI0 to ANI3
(3) Conflicting operations
To satisfy the DC characteristics of the supply current in the STOP mode, clear bit 7 (ADCS) and bit 0 (ADCE) of
the A/D converter mode register (ADM) to 0 before executing the STOP instruction.
Observe the rated range of the ANI0 to ANI3 input voltage. If a voltage of AV
in the range of absolute maximum ratings) is input to an analog input channel, the converted value of that channel
becomes undefined. In addition, the converted values of the other channels may also be affected.
<1> Conflict between A/D conversion result register (ADCR, ADCRH) write and ADCR, ADCRH read by
<2> Conflict between ADCR, ADCRH write and A/D converter mode register (ADM) write or analog input
instruction upon the end of conversion
ADCR, ADCRH read has priority. After the read operation, the new conversion result is written to ADCR,
ADCRH.
channel specification register (ADS) write upon the end of conversion
ADM or ADS write has priority. ADCR, ADCRH write is not performed, nor is the conversion end interrupt
signal (INTAD) generated.
CHAPTER 10 A/D CONVERTER
User’s Manual U16898EJ5V0UD
REF
or higher and V
SS
or lower (even
175
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