UPD78F9222MC(T)-5A4-A NEC, UPD78F9222MC(T)-5A4-A Datasheet - Page 394

• Manufacturer Part Number: UPD78F9222MC(T)-5A4-A
• Description: 8BIT MCU, 4K FLASH, 256B RAM, 78F9222
• Manufacturer: NEC

Specifications of UPD78F9222MC(T)-5A4-A

• Controller Family/series: UPD78
• No. Of I/o's: 17
• Ram Memory Size: 256Byte
• Cpu Speed: 10MHz
• No. Of Timers: 4
• No. Of: RoHS Compliant
• Core Size: 8bit
• Program Memory Size: 4KB
• Oscillator Type: External, Internal

394
Serial
interface
UART6
Function
ASIM6:
Registers
controlling
serial interface
UART6
ASIS6:
Asynchronous
serial interface
reception error
status register 6
ASIF6:
Asynchronous
serial interface
transmission
status register 6 To initialize the transmission unit upon completion of continuous transmission,
CKSR6: Clock
selection
register 6
BRGC6: Baud
rate generator
control register
6
ASICL6:
Asynchronous
serial interface
control register
6
Details of
Function
At startup, transmission operation is started by setting TXE6 to 1 after having
set POWER6 to 1, then setting the transmit data to TXB6 after having waited for
one clock or more of the base clock (f
operation, set POWER6 to 0 after having set TXE6 to 0.
At startup, reception enable status is entered by setting RXE6 to 1 after having
set POWER6 to 1 and one clock of the base clock (f
stopping reception operation, set POWER6 to 0 after having set RXE6 to 0.
Set POWER6 = 1 → RXE6 = 1 in a state where a high level has been input to
the RxD6 pin. If POWER6 = 1 → RXE6 = 1 is set during low-level input,
reception is started and correct data will not be received.
Clear the TXE6 and RXE6 bits to 0 before rewriting the PS61, PS60, and CL6 bits. p. 188
Fix the PS61 and PS60 bits to 0 when the interface is used for LIN
communication operation.
Make sure that TXE6 = 0 when rewriting the SL6 bit. Reception is always
performed with “the number of stop bits = 1”, and therefore, is not affected by
the set value of the SL6 bit.
Make sure that RXE6 = 0 when rewriting the ISRM6 bit.
The operation of the PE6 bit differs depending on the set values of the PS61
and PS60 bits of asynchronous serial interface operation mode register 6
(ASIM6).
The first bit of the receive data is checked as the stop bit, regardless of the
number of stop bits.
If an overrun error occurs, the next receive data is not written to receive buffer
register 6 (RXB6) but discarded.
Be sure to read ASIS6 before reading receive buffer register 6 (RXB6).
To transmit data continuously, write the first transmit data (first byte) to the
TXB6 register. Be sure to check that the TXBF6 flag is “0”. If so, write the next
transmit data (second byte) to the TXB6 register. If data is written to the TXB6
register while the TXBF6 flag is “1”, the transmit data cannot be guaranteed.
be sure to check that the TXSF6 flag is “0” after generation of the transmission
completion interrupt, and then execute initialization. If initialization is executed
while the TXSF6 flag is “1”, the transmit data cannot be guaranteed.
Make sure POWER6 = 0 when rewriting TPS63 to TPS60.
Make sure that bit 6 (TXE6) and bit 5 (RXE6) of the ASIM6 register = 0 when
rewriting the MDL67 to MDL60 bits.
The baud rate is the output clock of the 8-bit counter divided by 2.
ASICL6 can be refreshed (the same value is written) by software during a
communication operation (when bit 7 (POWER6) and bit 6 (TXE6) of ASIM6 are
1 or when bit 7 (POWER6) and bit 5 (RXE6) of ASIM6 are 1), if 0 data has been
written to ASICL6 by SBRT6 and SBTT6.
In the case of an SBF reception error, return to SBF reception mode again. The
status of the SBRF6 flag will be held (1). For details on SBF reception refer to
(2) – (i) SBF reception in 11.4.2 Asynchronous serial interface (UART) mode
described later.
APPENDIX D LIST OF CAUTIONS
User’s Manual U16898EJ5V0UD
Cautions
XCLK6
). When stopping transmission
XCLK6
) has elapsed. When
p. 188
p. 188
p. 188
p. 188
p. 188
p. 188
p. 188
pp. 188,
206
p. 189
p. 189
p. 190
p. 191
p. 191
p. 192
p. 193
p. 187
p. 188
Page
(11/19)